DXCCR (DDR_PHY) Register Description
| Register Name | DXCCR |
|---|---|
| Offset Address | 0x0000000088 |
| Absolute Address | 0x00FD080088 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x20000038 |
| Description | DATX8 Common Configuration Register |
DXCCR (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:30 | roRead-only | 0x0 | Returns zeroes on reads. Caution: Do not write to this register field. |
| RKLOOP | 29 | rwNormal read/write | 0x1 | Rank looping (per-rank eye centering) enable. Enables, if set, the read and write eye centering algorithms to be executed in a loop for all the system ranks, storing individual LCDL centering values for each rank. If this bit is not set, read and write centering are only executed for the configured DTCR0. DTRANK, although the result is replicated to all rank LCDLs |
| Reserved | 28:7 | roRead-only | 0x0 | Return zeroes on reads |
| DQS2DQMPER | 6:3 | rwNormal read/write | 0x7 | Write DQS2DQ training measurement period: Sets the tDQS2DQ delay measurement period. Valid values for measurement period are: 4`b0000: Disabled. 4`b0001: 16 clock cycles 4`b0010: 32 clock cycles 4`b0011: 64 clock cycles 4`b0100: 128 clock cycles 4`b0101: 256 clock cycles 4`b0110: 512 clock cycles 4`b0111: 2048 clock cycles 4`b1000: 4096 clock cycles 4`b1001: 8192 clock cycles Note: Valid values for DQS2DQMPER speed <= 533Mbps: Valid value are from 1 to 7 speed <= 1066Mbps: Valid value are from 1 to 8 speed > 1066Mbps: Valid values are from 1 to 9 |
| Reserved | 2:0 | roRead-only | 0x0 | Return zeroes on reads |