ECCBITMASK1 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ECCBITMASK1 (DDRC) Register Description

Register NameECCBITMASK1
Offset Address0x000000009C
Absolute Address 0x00FD07009C (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionECC Corrected Data Bit Mask Register 1

ECCBITMASK1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_corr_bit_mask_63_3231:0roRead-only0x0Mask for the corrected data portion
- 1 on any bit indicates that the bit has been corrected by the ECC logic
- 0 on any bit indicates that the bit has not been corrected by the ECC logic
This register accumulates data over multiple ECC errors, to give an overall indication of which bits are being fixed. It is cleared by writing a 1 to ECCCLR.ecc_clr_corr_err.
For 32-bit ECC, this register is not used.