ECCBITMASK2 (DDRC) Register Description
| Register Name | ECCBITMASK2 |
|---|---|
| Offset Address | 0x00000000A0 |
| Absolute Address | 0x00FD0700A0 (DDRC) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | ECC Corrected Data Bit Mask Register 2 |
ECCBITMASK2 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ecc_corr_bit_mask_71_64 | 7:0 | roRead-only | 0x0 | Mask for the corrected data portion - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates data over multiple ECC errors, to give an overall indication of which bits are being fixed. It is cleared by writing a 1 to ECCCLR.ecc_clr_corr_err. This register refers to the ECC byte, which is bits [71:64] for 64-bit ECC, [39:32] for 32-bit ECC. |