ECCCSYN1 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ECCCSYN1 (DDRC) Register Description

Register NameECCCSYN1
Offset Address0x0000000090
Absolute Address 0x00FD070090 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionECC Corrected Syndrome Register 1

ECCCSYN1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_corr_syndromes_63_3231:0roRead-only0x0Data pattern that resulted in a corrected error. For 32-bit ECC, this register is not used.