ECCCSYN2 (DDRC) Register Description
| Register Name | ECCCSYN2 |
|---|---|
| Offset Address | 0x0000000094 |
| Absolute Address | 0x00FD070094 (DDRC) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | ECC Corrected Syndrome Register 2 |
ECCCSYN2 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ecc_corr_syndromes_71_64 | 7:0 | roRead-only | 0x0 | Data pattern that resulted in a corrected error one for each ECC lane, all concatenated together This register refers to the ECC byte, which is bits [71:64] for 64-bit ECC, [39:32] for 32-bit ECC. |