ECCSTAT (DDRC) Register Description
| Register Name | ECCSTAT |
|---|---|
| Offset Address | 0x0000000078 |
| Absolute Address | 0x00FD070078 (DDRC) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | ECC Status Register |
ECCSTAT (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ecc_uncorrected_err | 19:16 | roRead-only | 0x0 | Double-bit error indicators, 1 per ECC lane. |
| ecc_corrected_err | 11:8 | roRead-only | 0x0 | Single-bit error indicators, 1 per data beat. ECCCADDR1 [ecc_corr_col] = 0: 0001: beat 0 0010: beat 1 0100: beat 2 1000: beat 3 ECCCADDR1 [ecc_corr_col] = 4: 0001: beat 4 0010: beat 5 0100: beat 6 1000: beat 7 |
| ecc_corrected_bit_num | 6:0 | roRead-only | 0x0 | Bit number (within the data beat) corrected by single-bit ECC error. If more than one data lane has an error, the lower data lane is selected. This register is 7 bits wide in order to handle 72 bits of the data present in a single lane. |