ECCUADDR1 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ECCUADDR1 (DDRC) Register Description

Register NameECCUADDR1
Offset Address0x00000000A8
Absolute Address 0x00FD0700A8 (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionECC Uncorrected Error Address Register 1

ECCUADDR1 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_uncorr_bg25:24roRead-only0x0Bank Group number of a read resulting in an uncorrected ECC error
ecc_uncorr_bank18:16roRead-only0x0Bank number of a read resulting in an uncorrected ECC error
ecc_uncorr_col11:0roRead-only0x0Block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here)