ECCUSYN0 (DDRC) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ECCUSYN0 (DDRC) Register Description

Register NameECCUSYN0
Offset Address0x00000000AC
Absolute Address 0x00FD0700AC (DDRC)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionECC Uncorrected Syndrome Register 0

ECCUSYN0 (DDRC) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ecc_uncorr_syndromes_31_031:0roRead-only0x0Data pattern that resulted in an uncorrected error, one for each ECC lane, all concatenated together.