ECR (CAN) Register Description
| Register Name | ECR |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address |
0x00FF060010 (CAN0) 0x00FF070010 (CAN1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Rx and Tx Error Counters |
The ECR is a read-only register. Writes to the ECR have no effect. The value of the error counters in the register reflect the values of the transmit and receive error counters in the CAN Protocol Engine Module (see Figure 1). The following conditions reset the Transmit and Receive Error counters: * When 1 is written to the SRST bit in the SRR * When 0 is written to the CEN bit in the SRR * When the CAN controller enters Bus Off state * During Bus Off recovery when the CAN controller enters Error Active state after 128 occurrences of 11 consecutive recessive bits When in Bus Off recovery, the Receive Error counter is advanced by 1 when a sequence of 11 consecutive recessive bits is seen.
ECR (CAN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:16 | roRead-only | 0x0 | Reserved |
| REC | 15:8 | roRead-only | 0x0 | Receive Error Counter Indicates the Value of the Receive Error Counter. |
| TEC | 7:0 | roRead-only | 0x0 | Transmit Error Counter Indicates the Value of the Transmit Error Counter. |