EDCIDSR (A53_DBG_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDCIDSR (A53_DBG_2) Register Description

Register NameEDCIDSR
Offset Address0x00000000A4
Absolute Address 0x00FEE100A4 (CORESIGHT_A53_DBG_2)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionExternal Debug Context ID Sample Register

EDCIDSR (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CONTEXTIDR31:0roRead-only0The sampled value of CONTEXTIDR_EL1, captured on reading the low half of EDPCSR.If EL3 is implemented and using AArch32 then CONTEXTIDR is a Banked register, and EDCIDSR samples the current Banked copy of CONTEXTIDR.