EDECCR (A53_DBG_2) Register Description
Register Name | EDECCR |
---|---|
Offset Address | 0x0000000098 |
Absolute Address | 0x00FEE10098 (CORESIGHT_A53_DBG_2) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | External Debug Exception Catch Control Register |
EDECCR (A53_DBG_2) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
NSE | 7:4 | rwNormal read/write | 0x0 | Coarse-grained Non-secure exception catch. Possible values of this field are:All other values are reserved. Bits [7,4] are reserved, RES0. |
SE | 3:0 | rwNormal read/write | 0x0 | Coarse-grained Secure exception catch. Possible values of this field are:All other values are reserved. Bits [2,0] are reserved. RES0. Ignored if ExternalSecureInvasiveDebugEnabled() == FALSE. |