EDECCR (A53_DBG_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDECCR (A53_DBG_3) Register Description

Register NameEDECCR
Offset Address0x0000000098
Absolute Address 0x00FEF10098 (CORESIGHT_A53_DBG_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExternal Debug Exception Catch Control Register

EDECCR (A53_DBG_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NSE 7:4rwNormal read/write0x0Coarse-grained Non-secure exception catch. Possible values of this field are:All other values are reserved. Bits [7,4] are reserved, RES0.
SE 3:0rwNormal read/write0x0Coarse-grained Secure exception catch. Possible values of this field are:All other values are reserved. Bits [2,0] are reserved. RES0. Ignored if ExternalSecureInvasiveDebugEnabled() == FALSE.