EDECR (A53_DBG_3) Register Description
| Register Name | EDECR |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FEF10024 (CORESIGHT_A53_DBG_3) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | External Debug Execution Control Register |
EDECR (A53_DBG_3) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SS | 2 | rwNormal read/write | 0x0 | Halting step enable. Possible values of this field are:If the value of EDECR.SS is changed when the processor is in Non-debug state, the resulting value of EDECR.SS is UNKNOWN. |
| RCE | 1 | rwNormal read/write | 0x0 | Reset catch enable. Possible values of this field are: |
| OSUCE | 0 | rwNormal read/write | 0x0 | OS unlock catch enabled. Possible values of this field are: |