EDESR (A53_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDESR (A53_DBG_0) Register Description

Register NameEDESR
Offset Address0x0000000020
Absolute Address 0x00FEC10020 (CORESIGHT_A53_DBG_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExternal Debug Event Status Register

EDESR (A53_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SS 2rwNormal read/write0x0Halting step debug event pending. Possible values of this field are:
RC 1rwNormal read/write0x0Reset catch debug event pending. Possible values of this field are:
OSUC 0rwNormal read/write0x0OS unlock debug event pending. Possible values of this field are: