EDITR (A53_DBG_3) Register Description
Register Name | EDITR |
---|---|
Offset Address | 0x0000000084 |
Absolute Address | 0x00FEF10084 (CORESIGHT_A53_DBG_3) |
Width | 32 |
Type | woWrite-only |
Reset Value | 0x00000000 |
Description | External Debug Instruction Transfer Register |
External Debug Instruction Transfer Register For 32-bit instructions: [15:0] is the first halfword of the T32 instruction to be executed on the processor. [31:16] is the second halfword of the T32 instruction to be executed on the processor. For 64-bit instrucitons: [31:0] is the A64 instruction to be executed on the processor.
EDITR (A53_DBG_3) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
T32Second_A64 | 31:16 | woWrite-only | 0 | Dual use, see above Note: Field name reference: T32Second |
T32First_A64 | 15:0 | woWrite-only | 0 | Dual use, see above Note: Field name reference: T32First |