EDITR (A53_DBG_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDITR (A53_DBG_3) Register Description

Register NameEDITR
Offset Address0x0000000084
Absolute Address 0x00FEF10084 (CORESIGHT_A53_DBG_3)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionExternal Debug Instruction Transfer Register

External Debug Instruction Transfer Register For 32-bit instructions: [15:0] is the first halfword of the T32 instruction to be executed on the processor. [31:16] is the second halfword of the T32 instruction to be executed on the processor. For 64-bit instrucitons: [31:0] is the A64 instruction to be executed on the processor.

EDITR (A53_DBG_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
T32Second_A6431:16woWrite-only0Dual use, see above
Note: Field name reference: T32Second
T32First_A6415:0woWrite-only0Dual use, see above
Note: Field name reference: T32First