EDPCSR_31to0 (A53_DBG_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDPCSR_31to0 (A53_DBG_2) Register Description

Register NameEDPCSR_31to0
Offset Address0x00000000A0
Absolute Address 0x00FEE100A0 (CORESIGHT_A53_DBG_2)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionExternal Debug Program Counter Sample Register (low word)

EDPCSR_31to0 (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EDPCSR_31to031:0roRead-only0PC Sample low word, EDPCSRlo. Bits [31:0] of the sampled instruction address value. Reading EDPCSRlo has the side-effect of updating EDCIDSR, EDVIDSR, and EDPCSRhi. However:If the processor is in Debug state, or Sample-based profiling is prohibited, EDPCSRlo reads as 0xFFFFFFFF and EDCIDSR, EDVIDSR, and EDPCSRhi become UNKNOWN.If the processor is in Reset state, the sampled value is unknown and EDCIDSR, EDVIDSR and EDPCSRhi become UNKNOWN.If no instruction has been retired since the processor left Reset state, Debug state, or a state where Non-invasive debug is not permitted, the sampled value is UNKNOWN and EDCIDSR, EDVIDSR, and EDPCSRhi become UNKNOWN.For a read of EDPCSRlo from the memory-mapped interface, if EDLSR.SLK == 1, meaning the Software Lock is locked, then the access has no side-effects. That is, EDCIDSR, EDVIDSR, and EDPCSRhi are unchanged.