Field Name | Bits | Type | Reset Value | Description |
COREPURQ | 3 | rwNormal read/write | 0 | Core powerup request. Allows a debugger to request that the power controller power up the core, enabling access to the debug register in the Core power domain. The actions on writing to this bit are:In an implementation that includes the recommended external debug interface, this bit drives the DBGPWRUPREQ signal.This bit can be read and written when the Core power domain is powered off.The power controller must not allow the Core power domain to switch off while this bit is one. |
CWRR | 1 | rwNormal read/write | 0x0 | Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are:The processor ignores writes to this bit if any of the following are the case:ExternalInvasiveDebugEnabled() == FALSE, EL3 is not implemented, and the processor is Non-secure.ExternalSecureInvasiveDebugEnabled() == FALSE and one of the following is true:EL3 is implemented.The processor is Secure.The Core power domain is either completely off or in a low-power state where the Core power domain registers cannot be accessed.DoubleLockStatus() == TRUE (OS Double Lock is set).OSLSR.OSLK == 1 (OS lock is locked).In an implementation that includes the recommended external debug interface, this bit drives the DBGRSTREQ signal. |
CORENPDRQ | 0 | rwNormal read/write | 0 | Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are: |