EDPRCR (A53_DBG_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDPRCR (A53_DBG_2) Register Description

Register NameEDPRCR
Offset Address0x0000000310
Absolute Address 0x00FEE10310 (CORESIGHT_A53_DBG_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExternal Debug Power/Reset Control Register

EDPRCR (A53_DBG_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
COREPURQ 3rwNormal read/write0Core powerup request. Allows a debugger to request that the power controller power up the core, enabling access to the debug register in the Core power domain. The actions on writing to this bit are:In an implementation that includes the recommended external debug interface, this bit drives the DBGPWRUPREQ signal.This bit can be read and written when the Core power domain is powered off.The power controller must not allow the Core power domain to switch off while this bit is one.
CWRR 1rwNormal read/write0x0Warm reset request. Write only bit that reads as zero. The actions on writing to this bit are:The processor ignores writes to this bit if any of the following are the case:ExternalInvasiveDebugEnabled() == FALSE, EL3 is not implemented, and the processor is Non-secure.ExternalSecureInvasiveDebugEnabled() == FALSE and one of the following is true:EL3 is implemented.The processor is Secure.The Core power domain is either completely off or in a low-power state where the Core power domain registers cannot be accessed.DoubleLockStatus() == TRUE (OS Double Lock is set).OSLSR.OSLK == 1 (OS lock is locked).In an implementation that includes the recommended external debug interface, this bit drives the DBGRSTREQ signal.
CORENPDRQ 0rwNormal read/write0Core no powerdown request. Requests emulation of powerdown. Possible values of this bit are: