| Field Name | Bits | Type | Reset Value | Description |
|---|
| SDR | 11 | roRead-only | 0 | Sticky debug restart. Set to 1 when the processor exits Debug state and cleared to 0 following reads of EDPRSR.This bit is UNKNOWN on reads if either of EDPRSR.{DLK, R} is 1, or EDPRSR.PU is 0.This bit clears to 0 when following a read of EDPRSR. |
| SPMAD | 10 | roRead-only | 0x0 | Sticky EPMAD error. Set to 1 if an access returns an error because AllowExternalPMUAccess() == FALSE.This bit is UNKNOWN on reads if either of EDPRSR.{DLK, R} is 1, or EDPRSR.PU is 0.This bit clears to 0 when following a read of EDPRSR. |
| EPMAD | 9 | roRead-only | 0 | External performance monitors access disable status.If external performance monitors access is not implemented, EPMAD is RAO. This bit is UNKNOWN on reads if either of EDPRSR.{DLK, R} is 1, or EDPRSR.PU is 0. |
| SDAD | 8 | roRead-only | 0x0 | Sticky EDAD error. Set to 1 if an access returns an error because AllowExternalDebugAccess() == FALSE.This bit is UNKNOWN on reads if either of EDPRSR.{DLK, R} is 1, or EDPRSR.PU is 0.This bit clears to 0 following a read of EDPRSR. |
| EDAD | 7 | roRead-only | 0 | External debug access disable status.This bit is UNKNOWN on reads if either of EDPRSR.{DLK, R} is 1, or EDPRSR.PU is 0. |
| DLK | 6 | roRead-only | 0 | OS Double Lock status bit.This bit is UNKNOWN on reads if EDPRSR.PU is 0. |
| OSLK | 5 | roRead-only | 0 | OS lock status bit. A read of this bit returns the value of OSLSR_EL1.OSLK.This bit is UNKNOWN on reads if either of EDPRSR.{DLK, R} is 1 or EDPRSR.PU is 0. |
| HALTED | 4 | roRead-only | 0 | Halted status bit. Possible values are:This bit is UNKNOWN on reads if EDPRSR.PU is 0. |
| SR | 3 | roRead-only | 0 | Sticky core reset status bit. Possible values are:This bit is UNKNOWN on reads if EDPRSR.DLK is 1 or EDPRSR.PU is 0.This bit clears to 0 following a read of EDPRSR if the non-debug logic of the processor is not in reset state. |
| R | 2 | roRead-only | 0 | Core reset status bit. Possible values are:This bit is UNKNOWN on reads if either EDPRSR.DLK is 1 or EDPRSR.PU is 0. |
| SPD | 1 | roRead-only | 0x1 | Sticky core power-down status bit.This bit is set to 1 on Cold reset to indicate the state of the debug registers has been lost. Since a Cold reset is required on powering up the processor, this usually indicates the Core power domain has been completely powered off.Possible values are:This bit is UNKNOWN on reads if both EDPRSR.DLK and EDPRSR.PU are 1.This bit clears to 0 following a read of EDPRSR if the processor is not in the powered down state. There are two logical power off states for the Core power domain:RetentionThe states of the debug registers, including EDPRSR.SPD, in the Core power domain is preserved, and restored on leaving retention state.Power-downThe states of the debug registers in the Core power domain is lost, and a Cold reset is asserted on leaving power-down state.In these states, it is IMPLEMENTATION DEFINED whether:EDPRSR.SPD shows whether the state of the debug registers in the Core power domain has been lost since the last time EDPRSR was read when the Core power domain was on.EDPRSR.SPD reads-as-zero.EDPRSR.SPD is not cleared following a read of EDPRSR in these states.This means it is IMPLEMENTATION DEFINED whether a processor implements EDPRSR.SPD as:Fixed RAZ when in one or both of the retention and power-down states.Retaining its previous value when in the retention state.Fixed RAO in the power-down state.Note that this definition does not allow EDPRSR.SPD to be fixed RAO in the low-power retention state, as the state of the debug registers in the Core power domain is not lost by entering this state. However, the bit can be read as 1 in this state if the state of the registers was lost before entering this state (i.e. EDPRSR has not been read since the last Cold reset).Arm recommends that an implementation make EDPRSR.SPD fixed RAO when in the power-down state, particularly if it does not support a low-power retention state. |
| PU | 0 | roRead-only | 0 | Core power-up status bit. Indicates whether the Core power domain debug registers can be accessed: |