EDSCR (A53_DBG_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDSCR (A53_DBG_3) Register Description

Register NameEDSCR
Offset Address0x0000000088
Absolute Address 0x00FEF10088 (CORESIGHT_A53_DBG_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionExternal Debug Status and Control Register

EDSCR (A53_DBG_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
RXfull30rwNormal read/write0x0DTRRX full. This bit is RO.
TXfull29rwNormal read/write0x0DTRTX full. This bit is RO.
ITO28rwNormal read/write0EDITR overrun. This bit is RO.If the processor is not in Debug state, this bit is UNKNOWN. ITO is set to 0 on entry to Debug state.
RXO27rwNormal read/write0x0DTRRX overrun. This bit is RO.
TXU26rwNormal read/write0x0DTRTX underrun. This bit is RO.
PipeAdv25rwNormal read/write0Pipeline advance. Read-only. Set to 1 every time the processor pipeline retires one or more instructions. Cleared to 0 by a write to EDRCR.CSPA.The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
ITE24rwNormal read/write0ITR empty. This bit is RO.If the processor is not in Debug state, this bit is UNKNOWN. It is always valid in Debug state.
INTdis23:22rwNormal read/write0x0Interrupt disable. Disables taking interrupts (including virtual interrupts and System Error interrupts) in Non-Debug state.If external invasive debug is disabled, the value of this field is ignored.If external invasive debug is enabled, the possible values of this field are:The value of INTdis does not affect whether an interrupt is a WFI wake-up event, but can mask an interrupt as a WFE wake-up event.If EL3 and EL2 are not implemented, INTdis[0] is RO and reads the same value as INTdis[1], meaning only the values 0b00 and 0b11 can be selected.
TDA21rwNormal read/write0x0Trap debug registers accesses.
MA20rwNormal read/write0x0Memory access mode. Controls use of memory-access mode for accessing EDITR and the DCC. This bit is ignored if in Non-debug state and set to zero on entry to Debug state.Possible values of this field are:
NS18rwNormal read/write0Non-secure status. Read-only. When in Debug state, gives the current security state:In Non-debug state, this bit is UNKNOWN.
SDD16rwNormal read/write0Secure debug disabled. This bit is RO.On entry to Debug state:If entering in Secure state, SDD is set to 0.If entering in Non-secure state, SDD is set to the inverse of ExternalSecureInvasiveDebugEnabled().In Debug state, the value of the SDD bit does not change, even if ExternalSecureInvasiveDebugEnabled() changes.In Non-debug state:SDD returns the inverse of ExternalSecureInvasiveDebugEnabled(). If the authentication signals that control ExternalSecureInvasiveDebugEnabled() change, a context synchronization operation is required to guarantee their effect.This bit is unaffected by the Security state of the processor.If EL3 is not implemented and the implementation is Non-secure, this bit is RES1.
HDE14rwNormal read/write0x0Halting debug mode enable. Possible values of this bit are:
RW13:10rwNormal read/write0Exception level register-width status. Read-only. In Debug state, each bit gives the current register width status of each EL:However:If not at EL0: RW[0] == RW[1].If EL2 is not implemented in the current security state: RW[2] == RW[1].If EL3 is not implemented: RW[3] == RW[2].In Non-debug state, this field is RAO.
EL 9:8rwNormal read/write0Exception level. Read-only. In Debug state, this gives the current EL of the processor.In Non-debug state, this field is RAZ.
A 7rwNormal read/write0System Error interrupt pending. Read-only. In Debug state, indicates whether a SError interrupt is pending:If HCR_EL2.{AMO, TGE} = {1, 0} and in Non-secure EL0 or EL1, a virtual SError interrupt.Otherwise, a physical SError interrupt.A debugger can read EDSCR to check whether a SError interrupt is pending without having to execute further instructions. A pending SError might indicate data from target memory is corrupted.UNKNOWN in Non-debug state.
ERR 6rwNormal read/write0x0Cumulative error flag. This field is RO. It is set to 1 following exceptions in Debug state and on any signaled overrun or underrun on the DTR or EDITR.
STATUS 5:0rwNormal read/write0Debug status flags. This field is RO.The possible values of this field are:All other values of STATUS are reserved.