EDVIDSR (A53_DBG_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDVIDSR (A53_DBG_0) Register Description

Register NameEDVIDSR
Offset Address0x00000000A8
Absolute Address 0x00FEC100A8 (CORESIGHT_A53_DBG_0)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionExternal Debug Virtual Context Sample Register

EDVIDSR (A53_DBG_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
NS31roRead-only0Non-secure state sample. Indicates the security state associated with the most recent EDPCSR sample.
E230roRead-only0Exception level 2 status sample. Indicates whether the most recent EDPCSR sample was associated with EL2. If EDVIDSR.NS == 0, this bit is 0.
E329roRead-only0Exception level 3 status sample. Indicates whether the most recent EDPCSR sample was associated with AArch64 EL3. If EDVIDSR.NS == 1 or the processor was in AArch32 state when EDPCSR was read, this bit is 0.
HV28roRead-only0EDPCSR high half valid. Indicates whether bits [63:32] of the most recent EDPCSR sample are valid. If EDVIDSR.HV == 0, the value of EDPCSR[63:32] is RAZ.
VMID 7:0roRead-only0VMID sample. The value of VTTBR_EL2.VMID associated with the most recent EDPCSR sample. If EDVIDSR.NS == 0 or EDVIDSR.E2 == 1, this field is RAZ.