EDWAR_31to0 (A53_DBG_2) Register Description
| Register Name | EDWAR_31to0 |
|---|---|
| Offset Address | 0x0000000030 |
| Absolute Address | 0x00FEE10030 (CORESIGHT_A53_DBG_2) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | External Debug Watchpoint Address Register (low word) |
EDWAR_31to0 (A53_DBG_2) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| EDWAR_31to0 | 31:0 | roRead-only | 0 | Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state, or if Debug state was entered other than for a watchpoint debug event.The address must be within a naturally-aligned block of memory of power-of-two size no larger than the DC ZVA block size. |