EDWAR_63to32 (A53_DBG_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EDWAR_63to32 (A53_DBG_3) Register Description

Register NameEDWAR_63to32
Offset Address0x0000000034
Absolute Address 0x00FEF10034 (CORESIGHT_A53_DBG_3)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionExternal Debug Watchpoint Address Register (high word)

EDWAR_63to32 (A53_DBG_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EDWAR_63to3231:0roRead-only0Watchpoint address. The virtual data address being accessed when a watchpoint debug event was triggered and caused entry to Debug state.UNKNOWN if the processor is not in Debug state, or if Debug state was entered other than for a watchpoint debug event.The address must be within a naturally-aligned block of memory of power-of-two size no larger than the DC ZVA block size.