EFUSE_AES_CRC (EFUSE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EFUSE_AES_CRC (EFUSE) Register Description

Register NameEFUSE_AES_CRC
Offset Address0x0000000048
Absolute Address 0x00FFCC0048 (EFUSE)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionEFUSE AES Key Integrity Check

EFUSE_AES_CRC (EFUSE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
AES_CRC_VALUE31:0woWrite-only0x0Writing the AES key CRC value to this register will start the AES integrity check. When the check is finished, the AES_CRC_DONE bit in the EFUSE_STATUS register will be set. If the value calculated by the EFUSE controller matches the value writen to this register, then the AES_CRC_PASS bit will also be set. The AES key must be cached in the EFUSE controller for this feature to work. After burning the key, reload the cache then write the CRC value to this register. The CRC check can be disabled by blowing the AES_RD_LOCK fuse.