ERR_CTRL (APU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ERR_CTRL (APU) Register Description

Register NameERR_CTRL
Offset Address0x0000000000
Absolute Address 0x00FD5C0000 (APU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionControl register

ERR_CTRL (APU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PSLVERR 0rwNormal read/write0x0Whether an APB access to an unimplemented register space causes PSLVERR