ERR_STATUS1 (XMPU_DDR) Register Description
| Register Name | ERR_STATUS1 |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address |
0x00FD000004 (DDR_XMPU0_CFG) 0x00FD010004 (DDR_XMPU1_CFG) 0x00FD020004 (DDR_XMPU2_CFG) 0x00FD030004 (DDR_XMPU3_CFG) 0x00FD040004 (DDR_XMPU4_CFG) 0x00FD050004 (DDR_XMPU5_CFG) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Error Status, Reg 1. |
The first AXI violation is recorded. Once a violation status flag is set in the ISR register, subsequent violations are not recorded. This register is reset by clearing a violation flag in the ISR register.
ERR_STATUS1 (XMPU_DDR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:28 | roRead-only | 0x0 | reserved |
| AXI_ADDR | 27:0 | roRead-only | 0x0 | Address bits from a poisoned read or write transaction. Bits [27:0] correspond to address bits [39:12]. Read-only. |