ERR_STATUS2 (XMPU_DDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ERR_STATUS2 (XMPU_DDR) Register Description

Register NameERR_STATUS2
Offset Address0x0000000008
Absolute Address 0x00FD000008 (DDR_XMPU0_CFG)
0x00FD010008 (DDR_XMPU1_CFG)
0x00FD020008 (DDR_XMPU2_CFG)
0x00FD030008 (DDR_XMPU3_CFG)
0x00FD040008 (DDR_XMPU4_CFG)
0x00FD050008 (DDR_XMPU5_CFG)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionError Status, Reg 2.

The first AXI violation is recorded. Once a violation status flag is set in the ISR register, subsequent violations are not recorded. This register is reset by clearing a violation flag in the ISR register.

ERR_STATUS2 (XMPU_DDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10roRead-only0x0reserved
AXI_ID 9:0roRead-only0x0Master ID from a poisoned read or write transaction.
Read-only.