| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| RSZ | 0x0000000004 | 32 | roRead-only | 0x00000800 | RAM size Register |
| STS | 0x000000000C | 32 | roRead-only | 0x00000000 | TMC Status register |
| RRD | 0x0000000010 | 32 | roRead-only | 0x00000000 | Reading this register enables data to be read from the trace memory. When the memory width given in the DEVID register is greater than 32 bits, multiple reads to this register must be performed together to read a full memory width of data. For example, if the memory width is 128 bits, then reads from this register must be performed four at a time. When a full memory width of data has been read, the RAM Read Pointer is incremented to the next memory word.When no data is available, this register returns 0xFFFFFFFF. This value is chosen because it cannot be generated as part of the trace data when the formatter is enabled.Trace Capture disabled: When in Disabled state (TraceCaptEn=0 and TMCReady=1), the TMC mode is ignored. Reading this register returns the contents of the Local RAM buffer or AXI memory at the location addressed by the RAM Read Pointer Register.Circular Buffer mode: When in Stopped state in Circular Buffer mode and the buffer is not empty, reading this register returns the next word of data from the trace buffer. When all of the trace buffer has been read, the Empty bit in the STS Register is set, and more reads return 0xFFFFFFF. Reading this register when not in Stopped state returns 0xFFFFFFFF.Software FIFO mode: Reading this register returns data from the FIFO. If this register is read when the FIFO is empty, the data returned is 0xFFFFFFFF.Hardware FIFO mode: Reading this register returns 0xFFFFFFFF.Reading this register alters the internal state of the TMC, and can only be performed if the device is unlocked. Reading this register when the device is locked returns 0xFFFFFFFF.In the ETR configuration, when the MemErr bit in the STS Register is set, reading this register returns an error response on the APB slave interface. |
| RRP | 0x0000000014 | 32 | rwNormal read/write | 0x00000000 | The RAM Read Pointer Register contains the value of the read pointer that is used to read entries from the trace memory over the APB interface.The value written to this register must be a byte-address aligned to the width of the trace memory databus and to a frame boundary. For example, for 64_bit wide trace memory and 128_bit wide trace memory, the four LSBs must be 0s. For 256_bit wide trace memory, the five LSBs must be 0s. The width of the trace memory can be obtained by reading the MEMWIDTH field in the DEVID Register, 0xFC8. When one complete buffer or FIFO entry has been read through the RRD Register, the RAM Read Pointer Register is incremented by the number of bytes per memory width of data. For example, for 64_bit wide memory, it is incremented by eight. For 128_bit wide memory, it is incremented by 16 for every complete memory entry read. When the RAM Read Pointer is incremented after having reached its maximum value, it wraps around. The width of this register in the ETB or ETF configurations is log2(MEM_SIZE*4). In the ETR configuration, this register is 32 bits wide, and the contents of this register represents the lower 32 bits of the 40-bit AXI address used to access trace memory. If scatter-gather operation is enabled, this register represents the next address in trace memory to be read, not the address of a page table entry. When in Disabled state (TraceCaptEn=0 and TMCReady=1), a write to this register sets the value of the trace memory address from which data is fetched on a subsequent RRD read. A write to this register when not in Disabled state results in Unpredictable behavior. This register can be read:<ul><li>when in Disabled state</li><li>when in Stopped state (TraceCaptEn=1 and TMCReady=1), in Circular Buffer mode</li><li>when in Running (TraceCaptEn=1 and TMCReady=0), Stopping or Stopped states, in Software FIFO mode.</li></ul>When entering Disabled state in Circular Buffer mode with scatter-gather mode disabled, this register points to the next location in the trace buffer to be read. This is for backwards compatibility purposes, so that the buffer can be read while in Disabled state. It is recommended that you read the buffer contents while in Stopped state instead, because the pointers are managed automatically. |
| RWP | 0x0000000018 | 32 | rwNormal read/write | 0x00000000 | The value written to this register must be a byte-address aligned to the width of the trace memory databus and to a frame boundary. For example, for 64_bit wide trace memory and 128_bit wide trace memory, the four LSBs must be 0s. For 256_bit wide trace memory, the five LSBs must be 0s. The width of the trace memory can be obtained by reading the MEMWIDTH field in the DEVID Register, 0xFC8. Reading this register returns the current memory location being referenced, to which the next write would occur. When one complete buffer or FIFO entry has been written to the RWD Register, the RAM Write Pointer Register is incremented by the number of bytes per memory width of data. For example, for 64_bit wide memory, it is incremented by eight. For 128_bit wide memory it is incremented by 16 for every complete memory entry write. When this register wraps around its maximum value, the Full flag in the Status Register, STS, 0x00C, is set. In the ETB or ETF configurations, the width of this register is log2(MEM_SIZE*4). In the ETR configuration, this register is 32 bits wide, and the contents of this register represent the lower 32 bits of the 40-bit AXI address used to access trace memory. In ETB and ETF configurations, when in Circular Buffer mode, this register can be used to set the address to start capturing data from. This is for backwards compatibility purposes, to enable the FULL signal to be generated before the buffer becomes full. In other configurations and modes, the RAM Write Pointer is reset to the start of trace memory when exiting Disabled state (TraceCaptEn=0 and TMCReady=1). This register can be read:<ul><li>when in Disabled state</li><li>when in Stopped state, in Circular Buffer mode</li><li>when in Running, Stopping or Stopped states, in Software FIFO mode.</li></ul> |
| TRG | 0x000000001C | 32 | rwNormal read/write | 0x00000000 | In the Circular-buffer mode, the Trigger Counter Register specifies the number of 32_bit words to capture in the Trace RAM following the detection of either a rising edge on the TRIGIN input or a trigger packet in the incoming trace stream (ATID = 7h7D). On capturing the specified number of datawords, a Trigger Event is said to have occurred. The effect of a Trigger Event on TMC behavior is controlled by the FFCR register, 0x304.The number of 32_bit words written into the Trace RAM following the trigger is the value stored in this register+1. This counter is disabled when the TMC is in Software-read-FIFO mode or Hardware-read-FIFO mode.Once the trigger counter has started counting, any further triggers, either on TRIGIN or in the incoming trace stream, are ignored till the counter reaches 0. Once the counter has reached 0, it remains at 0 till it is re-programmed with a write to this register. This register is cleared when TMCReady goes HIGH, so that the state of the counter when trace capture has stopped does not affect a subsequent trace capture cycle.Attempting to write to this register while not in Disabled state (TMCReady=0 or TraceCaptEn=1) will result in Unpredictable behavior. A read access to this register is permitted even if trace capture enabled. A read access returns the current value of the Trigger counter. The width of this register and the Trigger counter depends on the size of the trace memory. In ETB and ETF configurations, the width of the counter is log2(MEMSIZE). The width of this register in ETR configuration is 32 bits. |
| CTL | 0x0000000020 | 32 | rwNormal read/write | 0x00000000 | This register controls trace stream capture.Setting the TraceCaptEn bit to 1 enables the TMC to capture trace data. When trace capture is enabled, Formatter behavior is controlled by the FFCR register.When trace capture is disabled, any remaining data in the formatter is stored to RAM. If the TMC is programmed for Software-read-FIFO mode or hardware-read-FIFO mode and and TraceCaptEn is cleared before TMCReady=1, trace data may get corrupted. In the Hardware-read-FIFO mode, the unformatter drains any trace data in its internal pipelines on to the ATB Master interface, but discards any data that remains in the trace FIFO. Trace capture is fully disabled, or complete, when TMCReady goes HIGH. See Formatter and Flush Status Register, FFSR, 0x300.It is recommended that stopping trace capture be initiated only by programming stop conditions in FFCR register bits. Stopping trace capture by clearing TraceCaptEn is deprecated and is supported only for backwards compatibility with earlier versions of the ETB. Features in the TMC such as the DrainBuffer bit (FFCR register) and the Empty bit (STS register) that are not part of the earlier versions of the ETB do not support stopping trace capture by clearing TraceCaptEn. If trace capture stopping is initiated by clearing this bit, then the DrainBuffer feature (ETF configuration) cannot be invoked. Also, in the ETR configuration, if the TMC is programmed for Scatter_Gather operation and Circular-Buffer mode, clearing TraceCaptEn prevents reading trace data from memory. |
| RWD | 0x0000000024 | 32 | woWrite-only | 0x00000000 | Enables testing of Trace RAM connectivity to the TMC. When in Disabled state (TraceCaptEn=0 and TMCReady=1), a write to this register stores data at the location pointed to by the RWP. Writes to this register when not in Disabled state are ignored. When the memory width given in the DEVID register is greater than 32_bit, multiple writes to this register must be performed together to read a full memory width of data. For example, if the memory width is 128 bits, then writes to this register must be performed four at a time. When a full memory width of data has been written, the data is written to memory and the RAM Write Pointer is incremented to the next memory word. In ETR configuration, when the MemErr bit in the STS Register is set, writing to this register returns an error response on the APB slave interface and the write data is discarded. Writing to this register other than when in Disabled state and in integration mode results in Unpredictable behavior. |
| MODE | 0x0000000028 | 32 | rwNormal read/write | 0x00000000 | Controls TMC operating mode. When configured as an ETB or ETR, the TMC can operate in the following modes:<ul><li>Software FIFO mode</li><li>Circular Buffer mode.</li></ul> When configured as an ETF, the TMC has an additional mode of operation, Hardware FIFO mode. The operating mode can be changed only when the TMC is disabled. Attempting to write to this register while not in Disabled state (TraceCaptEn=0 and TMCReady=1) results in Unpredictable behavior. The operating mode is ignored when in Disabled state. |
| LBUFLEVEL | 0x000000002C | 32 | roRead-only | 0x00000000 | Reading this register returns the maximum fill level of the trace memory in 32_bit words since this register was last read. Reading this register also results in its contents being updated to the current fill level.This register does not apply when the TMC is programmed for Scatter Gather operation in ETR configuration. In this case, reading this register will return 0x00000000.When the TraceCaptEn bit is cleared, this register retains it last value. If TraceCaptEn is 0 and a 1 is written to it, the LBUFLEVEL register is cleared.The fill level information is mainly useful for performance analysis.Reading this register alters the internal state of the TMC, hence this register can be read only if the device is unlocked. Reading this register when the device is locked will return 0x00000000.The width of this register in the ETB/ETF configurations is 1+log2(MEM_SIZE). In the ETR configuration, the width of this register is 31 bits. Note that an extra bit is needed to return the correct fill level when full. |
| CBUFLEVEL | 0x0000000030 | 32 | roRead-only | 0x00000000 | When TraceCaptEn=1, this register indicates the current fill level of the trace memory in 32_bit words. When TraceCaptEn=0, reading this register returns a value of 0x00000000. This register is not available if the TMC is programmed for Scatter_Gather operation in ETR configuration - in this case, reading this register returns a value of 0x00000000. This register is particularly useful in the FIFO modes, in which the pointers change dynamically due to read and write of trace data into trace memory through hardware. It would not be possible for the debugger to deduce the fill level of the trace memory merely by reading the pointer registers. The fill level information is mainly useful for performance analysis. |
| BUFWM | 0x0000000034 | 32 | rwNormal read/write | 0x00000000 | The value programmed into this register indicates the desired threshold vacancy level in 32_bit words in the trace memory. When the space into FIFO is less than or equal to this value (ie Fill level >= MEM_SIZE - BUFWM), the FULL output is pulled HIGH and the Full bit in the STS register is set. This register is used only in the Software FIFO mode and the Hardware FIFO mode. In the Circular Buffer mode, this functionality can be obtained by programming the RWP to the desired vacancy trigger level, so that when the pointer wraps around, the Full bit is set indicating that the vacancy level has fallen below the desired level. The maximum value that can be written into this register is MEM_SIZE - 1 (in which case the Full bit is set after the first 32_bit word is written to trace memory.).Writing to this register other than when TMCReady=1 and TraceCaptEn=0 will result in Unpredictable behavior.This register is ignored when the TMC is programmed for scatter-gather operation in ETR configuration. |
| FFSR | 0x0000000300 | 32 | roRead-only | 0x00000000 | This register indicates the status of the Formatter and the status of Flush request. |
| FFCR | 0x0000000304 | 32 | rwNormal read/write | 0x00000000 | This register allows user control of the stop, trigger, and flush events. When the EnFt bit is 0, no formatting information is inserted into the trace stream and the trace data is stored raw. When tracing is stopped, a byte of value 0x01 is appended to the trace buffer, followed by zero or more bytes of value 0x00 to align to a memory dataword. When data is later decompressed it is then possible to determine that a post-amble is present by back tracking the trailing zero data at the end of the trace stream until the last single bit at logic 1 is detected. All data preceding this first logic 1 is then treated as decompressible data. When all data has been stored in the RAM, FtStopped in the Formatter and Flush Status Register is set HIGH. Note: When the EnFt bit is 0, it is assumed that the source ID is not changing. Multiple flush generating conditions can be enabled together. However, if a second or third flush event is generated then the current flush completes before the next flush is serviced. Only one flush can be outstanding at a time. If two flushes are requested simultaneously, only one will be issued. If two flushes are requested while another is in progress, only one further flush will be issued when the in-progress flush completes.Multiple trigger indication conditions can be enabled simultaneously although this can cause the appearance of multiple triggers if flush using trigger is also enabled. If StopOnTrigEvt and FOnTrigEvt are both set then none of the flushed data is stored. When the system stops, it returns ATREADYS HIGH and does not store the accepted data packets. This is to stop stalling of any other devices connected using a Trace Replicator. StopOnTrigEvt, FOnTrigEvt and TrigOnTrigEvt bits are functional only in Circular Buffer mode. Setting these bits with the TMC enabled in FIFO modes will not have any effect on the TMC.Note: To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required - one to enable the stop event, if it is not already enabled and one to generate the manual flush. |
| PSCR | 0x0000000308 | 32 | rwNormal read/write | 0x00000000 | This register determines the reload value of the Periodic Synchronization Counter. This counter enables the frequency of synchronization information to be optimized to the trace capture buffer size.When the TMC is enabled, the Periodic Synchronization counter counts the number of bytes of trace data stored into the trace memory (regardless of whether the trace data has been formatted by the TMC or not) since the occurrence of the last synchronization request on the ATB slave interface. The value programmed into this register determines the reload value of the Periodic Synchronization counter.This counter is enabled only when the TraceCaptEn bit in the Control Register, CTL, 0x020, is set. Writing to this register other than when TraceCaptEn=0 and TMCReady=1 will result in Unpredictable behavior. |
| ITATBMDATA0 | 0x0000000ED0 | 32 | woWrite-only | 0x00000000 | The Integration Test ATB Master Data Register 0 enables control of the ATDATAM output of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
| ITATBMCTR2 | 0x0000000ED4 | 32 | roRead-only | 0x00000000 | The Integration Test ATB Master Interface Control Register 2 captures the values of the SYNCREQM, AFVALIDM and ATREADYM inputs to the TMC. |
| ITATBMCTR1 | 0x0000000ED8 | 32 | woWrite-only | 0x00000000 | The Integration Test ATB Master Control Register 1 enables control of the ATIDM outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
| ITATBMCTR0 | 0x0000000EDC | 32 | woWrite-only | 0x00000000 | The Integration Test ATB Master Interface Control Register 0 enables control of the ATBYTESM, AFREADYM and ATVALIDM outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
| ITMISCOP0 | 0x0000000EE0 | 32 | woWrite-only | 0x00000000 | The Integration Test Miscellaneous Output Register 0 controls the values of some outputs from the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
| ITTRFLIN | 0x0000000EE8 | 32 | roRead-only | 0x00000000 | This register returns the values of the FLUSHIN and TRIGIN inputs to the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
| ITATBDATA0 | 0x0000000EEC | 32 | roRead-only | 0x00000000 | The Integration Test ATB Data Register 0 returns the values on the ATDATAS input to the TMC. |
| ITATBCTR2 | 0x0000000EF0 | 32 | woWrite-only | 0x00000000 | The Integration Test ATB Control Register 2 enables control of the ATREADYS and AFVALIDS outputs of the TMC. Writing to this register other than when in Disabled state (TraceCaptEn=0 and TMCReady=1) and in integration mode results in Unpredictable behavior. |
| ITATBCTR1 | 0x0000000EF4 | 32 | roRead-only | 0x00000000 | The Integration Test ATB Control Register 1 captures the value of the ATIDS input to the TMC. |
| ITATBCTR0 | 0x0000000EF8 | 32 | roRead-only | 0x00000000 | The Integration Test ATB Control Register 0 captures the values of the ATVALIDS, AFREADYS and ATBYTESS inputs to the TMC. |
| ITCTRL | 0x0000000F00 | 32 | rwNormal read/write | 0x00000000 | This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving. Note: When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection.Writing to this register other than when in Disabled state (TMCReady=1 and TraceCaptEn=0) results in Unpredictable behavior. |
| CLAIMSET | 0x0000000FA0 | 32 | rwNormal read/write | 0x00000000 | This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read. |
| CLAIMCLR | 0x0000000FA4 | 32 | rwNormal read/write | 0x00000000 | This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read. |
| LAR | 0x0000000FB0 | 32 | woWrite-only | 0x00000000 | This is used to enable write access to device registers. External accesses from a debugger (PADDRDBG31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the component. |
| LSR | 0x0000000FB4 | 32 | roRead-only | 0x00000000 | This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked, write access is blocked to all registers, except the Lock Access Register.External accesses from a debugger (PADDRDBG31 = 1) are not subject to the Lock Registers. This register reads as 0 when read from an external debugger (PADDRDBG31 = 1). |
| AUTHSTATUS | 0x0000000FB8 | 32 | roRead-only | 0x00000000 | Reports what functionality is currently permitted by the authentication interface. |
| DEVID | 0x0000000FC8 | 32 | roRead-only | 0x00000000 | This register indicates the capabilities of the CoreSight TMC. |
| DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000000 | It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. |
| PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator. |
| PIDR5 | 0x0000000FD4 | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR6 | 0x0000000FD8 | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR7 | 0x0000000FDC | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number. |
| PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity. |
| PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision. |
| PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields. |
| CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x0000000D | A component identification register, that indicates that the identification registers are present. |
| CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000090 | A component identification register, that indicates that the identification registers are present. This register also indicates the component class. |
| CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000005 | A component identification register, that indicates that the identification registers are present. |
| CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x000000B1 | A component identification register, that indicates that the identification registers are present. |