EVCNTR2_EL0 (A53_PMU_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EVCNTR2_EL0 (A53_PMU_2) Register Description

Register NameEVCNTR2_EL0
Offset Address0x0000000010
Absolute Address 0x00FEE30010 (CORESIGHT_A53_PMU_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPerformance Monitors Event Count Registers

EVCNTR2_EL0 (A53_PMU_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EVCNTR2_EL031:0rwNormal read/write0x0Event counter n. Value of event counter n, where n is the number of this register and is a number from 0 to 30.