EVENTCTL1R (A53_ETM_0) Register Description
| Register Name | EVENTCTL1R |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FEC40024 (CORESIGHT_A53_ETM_0) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Event Control 1 Register |
EVENTCTL1R (A53_ETM_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| LPOVERRIDE | 12 | rwNormal read/write | 0x0 | Low power state behavior override: 0=low poer state behavior unaffected, 1=low power state overriden. The resources and Event trace generation are unaffected by entry to a low power state |
| ATB | 11 | rwNormal read/write | 0x0 | ATB trigger enable |
| EN | 3:0 | rwNormal read/write | 0x0 | One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs |