EXTCTL_Out_Port (TPIU) Register Description
| Register Name | EXTCTL_Out_Port |
|---|---|
| Offset Address | 0x0000000404 |
| Absolute Address | 0x00FE980404 (CORESIGHT_SOC_TPIU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexors or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. The output register bank is set to all zeros on reset. The input registers sample the incoming signals and as such are undefined. |
EXTCTL_Out_Port (TPIU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| extctlout | 7:0 | rwNormal read/write | 0x0 | EXTCTL Outputs. Bits [7:1] are not used; bit [0] controls the source for TPIU trace clock: 0: trace clock is from PS clock controller 1: trace clock is from PL |