EXTENDED_IDCODE (EFUSE) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

EXTENDED_IDCODE (EFUSE) Register Description

Register NameEXTENDED_IDCODE
Offset Address0x0000001018
Absolute Address 0x00FFCC1018 (EFUSE)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionAvailable Functionality

The device family can be determined using the VCU_DIS & GPU_DIS bits: 00: EV (includes VCU and GPU) 01: Invalid 10: EG (includes GPU) 11: CG (no VCU or GPU; 2-core)

EXTENDED_IDCODE (EFUSE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
VCU_DIS 8roRead-only0x00: VCU is present
1: VCU is not present
Note:this bit is only valid if the PL is powered-up and the PROG_B signal is released.
GPU_DIS 5roRead-only0x00: GPU is present
1: GPU is not present
APU3_DIS 3roRead-only0x0Indicates that APU core 3 is disabled if set
APU2_DIS 2roRead-only0x0Indicates that APU core 2 is disabled if set
APU1_DIS 1roRead-only0x0Indicates that APU core 1 is disabled if set
APU0_DIS 0roRead-only0x0Indicates that APU core 0 is disabled if set