E_BREG_CONTROL (AXIPCIE_MAIN) Register Description
| Register Name | E_BREG_CONTROL |
|---|---|
| Offset Address | 0x0000000208 |
| Absolute Address | 0x00FD0E0208 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000002 |
| Description | Egress Bridge Register Translation - Control |
E_BREG_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:18 | roRead-only | 0x0 | |
| breg_size | 17:16 | rwNormal read/write | 0x0 | Size of this translation window, expressed as 2^(breg_size_offset+breg_size). Constrained by the breg_size_max and breg_size_offset fields. |
| Reserved | 15:3 | roRead-only | 0x0 | |
| breg_security_enable | 2 | rwNormal read/write | 0x0 | Translation security enable/disable. |
| breg_enable_force | 1 | rwNormal read/write | 0x1 | Force all AXI Slave Interface transactions to be claimed by the Egress Bridge Register Translation. |
| breg_enable | 0 | rwNormal read/write | 0x0 | Translation Enable. The translation is hit when both of the following are true: * breg_enable == 1 * breg_src_base[63:(12+breg_size)] == AXI Address[63:(12+breg_size)] |