E_DREG_BASE_HI (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

E_DREG_BASE_HI (AXIPCIE_MAIN) Register Description

Register NameE_DREG_BASE_HI
Offset Address0x0000000294
Absolute Address 0x00FD0E0294 (AXIPCIE_MAIN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEgress DMA Register Translation - Source Address High

E_DREG_BASE_HI (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dma_base_hi31:0rwNormal read/write0x0This field must be set to 0x0