E_DREG_BASE_LO (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

E_DREG_BASE_LO (AXIPCIE_MAIN) Register Description

Register NameE_DREG_BASE_LO
Offset Address0x0000000290
Absolute Address 0x00FD0E0290 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEgress DMA Register Translation - Source Address Low

E_DREG_BASE_LO (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dma_base_lo31:12rwNormal read/write0x0This field must be set to 0xFD0F0
Reserved11:0roRead-only0x0