E_DREG_CAPABILITIES (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

E_DREG_CAPABILITIES (AXIPCIE_MAIN) Register Description

Register NameE_DREG_CAPABILITIES
Offset Address0x0000000280
Absolute Address 0x00FD0E0280 (AXIPCIE_MAIN)
Width32
TyperoRead-only
Reset Value0x030C0001
DescriptionEgress DMA Register Translation - Capabilities

E_DREG_CAPABILITIES (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
dma_size_max31:24roRead-only0x3dma_size supports values between 0 and dma_size_max. Maximum translation size is 2^(dma_size_offset+dma_size_max).
dma_size_offset23:16roRead-only0xCMinimum translation size is 2^(dma_size_offset).
Reserved15:1roRead-only0x0
dma_present 0roRead-only0x1Translation presence indicator.