E_DREG_CONTROL (AXIPCIE_MAIN) Register Description
| Register Name | E_DREG_CONTROL |
|---|---|
| Offset Address | 0x0000000288 |
| Absolute Address | 0x00FD0E0288 (AXIPCIE_MAIN) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Egress DMA Register Translation - Control |
E_DREG_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:18 | roRead-only | 0x0 | |
| dma_size | 17:16 | rwNormal read/write | 0x0 | Size of this translation window, expressed as 2^(dma_size_offset+dma_size). Constrained by the dma_size_max and dma_size_offset fields.Note: the dma size is in bytes. |
| Reserved | 15:3 | roRead-only | 0x0 | |
| dma_security_enable | 2 | rwNormal read/write | 0x0 | Translation security enable/disable. |
| Reserved | 1 | roRead-only | 0x0 | |
| dma_enable | 0 | rwNormal read/write | 0x0 | Translation Enable. The translation is hit when both of the following are true: * dma_enable == 1 * dma_src_base[63:(12+dma_size)] == AXI Address[63:(12+dma_size)] |