E_MSXP_CONTROL (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

E_MSXP_CONTROL (AXIPCIE_MAIN) Register Description

Register NameE_MSXP_CONTROL
Offset Address0x0000000268
Absolute Address 0x00FD0E0268 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEgress MSI-X PBA Translation - Control

E_MSXP_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:18roRead-only0x0
msxp_size17:16rwNormal read/write0x0Size of this translation window, expressed as 2^(msxp_size_offset+msxp_size). Constrained by the msxp_size_max and msxp_size_offset fields.
Reserved15:3roRead-only0x0
msxp_security_enable 2rwNormal read/write0x0Translation security enable/disable.
Reserved 1roRead-only0x0
msxp_enable 0rwNormal read/write0x0Translation Enable. The translation is hit when both of the following are true:
* msxp_enable == 1
* msxp_src_base[63:(12+msxp_size)] == AXI Address[63:(12+msxp_size)]