Event_Counter0_Control (CCI400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Event_Counter0_Control (CCI400) Register Description

Register NameEvent_Counter0_Control
Offset Address0x000000A008
Absolute Address 0x00FD6EA008 (CCI_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEvent_Counter0_Control

Event_Counter0_Control (CCI400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CNT0_EN 0rwNormal read/write0x0Enable event counter 0