Event_Counter0_Overflow (CCI400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Event_Counter0_Overflow (CCI400) Register Description

Register NameEvent_Counter0_Overflow
Offset Address0x000000A00C
Absolute Address 0x00FD6EA00C (CCI_GPV)
Width32
TypewtcReadable, write a 1 to clear
Reset Value0x00000000
DescriptionEvent_Counter0_Overflow

Event_Counter0_Overflow (CCI400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CNT0_OVERFLOW 0wtcReadable, write a 1 to clear0x0Event counter 0 overflow flag