FEAT2R (STM) Register Description
| Register Name | FEAT2R |
|---|---|
| Offset Address | 0x0000000EA4 |
| Absolute Address | 0x00FE9C0EA4 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Read the features of the STM. |
FEAT2R (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SPTYPE | 17:16 | roRead-only | 0x0 | Stimulus port type support: 1: Extended only. |
| DSIZE | 15:12 | roRead-only | 0x0 | Fundamental data size: 1: 64-bit. |
| SPTRTYPE | 10:9 | roRead-only | 0x0 | Stimulus port transaction type support: 2: invariant timing and Guaranteed. |
| PRIVMASK | 8:7 | roRead-only | 0x0 | STMPRIVMASKR support: 1: not implemented. |
| SPOVERRIDE | 6 | roRead-only | 0x0 | STMOVERRIDER support: 1: implemented. |
| SPCOMP | 5:4 | roRead-only | 0x0 | Data compression on stimulus ports support: 3: programmable. |
| SPER | 2 | roRead-only | 0x0 | STMSPER presence: 0: implemented. |
| SPTER | 1:0 | roRead-only | 0x0 | STMSPTER support: 2: implemented. |