| Field Name | Bits | Type | Reset Value | Description |
|---|
| DrainBuffer | 14 | rwNormal read/write | 0x0 | This bit is used to enable draining of the trace data through the ATB Master interface after the formatter has stopped. This is useful in Circular buffer mode to capture trace data into trace memory and then drain the captured trace through the ATB Master interface. Writing a 1 to this bit when TMCReady=1 and TraceCaptEn=1 starts the drain of the contents of the trace buffer through the ATB Master interface. This bit always reads as zero. The TMCReady bit (STS register, 0x00C) goes low while the drain is in progress.This bit is functional only when the TMC is in Circular Buffer mode and formatting is enabled (EnFt bit in FFCR register is set). Setting this bit when the TMC is in any other mode or when formatting is disabled will result in Unpredictable behavior.Setting this bit other than when the TMCReady bit (STS Register, 0x00C) is set and TraceCaptEn=1 will result in Unpredictable behavior. Once trace capture is complete in Circular Buffer mode, all of the captured trace must be retrieved from the trace memory through the same mechanism - either read all trace data out through RRD reads or drain all trace data by setting the DrainBuffer bit. Setting the DrainBuffer bit after some of the captured trace has been read out through RRD will result in Unpredictable behavior. |
| StopOnTrigEvt | 13 | rwNormal read/write | 0x0 | If this bit is set, the formatter is stopped when a Trigger Event has been observed. A Trigger Event is said to have occurred when the Formatter has written the set number of datawords (as programmed in the TRG register, 0x01C) into the trace memory after the occurrence of either a rising edge on the TRIGIN input or a trigger packet on the incoming trace stream (ATID = 7h7D). This bit is cleared on reset (disabled). Enabling the TMC in Software-read-FIFO mode or Hardware-read-FIFO mode with this bit set will result in Unpredictable behavior because in FIFO modes, the TMC is a trace link rather than a trace sink and trigger events are related to trace sink functionality. |
| StopOnFl | 12 | rwNormal read/write | 0x0 | If this bit is set, the formatter is stopped on completion of a flush operation. The initiation of a flush operation is controlled by programming the register bits FlushMan, FOnTrigEvt and FOnFlIn in the FFCR register, 0x304. When a flush-initiation condition occurs, AFVALIDS is pulled HIGH. Once AFREADYS is sampled HIGH, trace capture is stopped. Any remaining data in the formatter is appended with a post-amble and written to trace memory. The flush operation is then said to have completed. This bit is cleared on reset (disabled).In the FIFO modes, if a flush is initiated due to any condition other than a manual flush request, its completion does not lead to a formatter stop regardless of the value programmed in this bit. When the TMC is configured as an ETF, if a flush is initiated by the ATB Master interface, its completion does not lead to a formatter stop regardless of the value programmed in this bit. |
| TrigOnFl | 10 | rwNormal read/write | 0x0 | If this bit is set, a trigger is indicated on the trace stream on AFREADYS being returned.If the formatter is bypassed (FFCR[0] = 0) or if Trigger Insertion is disabled (FFCR[1] = 0), then trigger indication on the trace stream is blocked regardless of the value programmed in this bit.When the TMC is configured as an ETF, if a flush is initiated by the ATB Master interface, its completion does not lead to a trigger indication on the trace stream regardless of the value programmed in this bit. |
| TrigOnTrigEvt | 9 | rwNormal read/write | 0x0 | If this bit is set, a trigger is indicated on the output trace stream when a Trigger Event occurs. A trigger event is said to have occurred when the Formatter has written the set number of datawords (as programmed in the TRG register) into the trace memory after the occurrence of either a rising edge on the TRIGIN input or a trigger packet in the incoming trace stream (ATID = 7h7D).If the formatter is bypassed (FFCR[0] = 0) or if Trigger Insertion is disabled (FFCR[1] = 0), then trigger indication on the trace stream is blocked regardless of the value programmed in this bit. This bit is not supported in Software-read-FIFO mode or Hardware-read-FIFO mode because in FIFO modes, the TMC is a trace link rather than a trace sink and trigger events are related to trace sink functionality. |
| TrigOnTrigIn | 8 | rwNormal read/write | 0x0 | If this bit is set, a trigger is indicated on the trace stream when a rising edge is detected on the TRIGIN input. If the formatter is bypassed (FFCR[0] = 0) or if Trigger Insertion is disabled (FFCR[1] = 0), then trigger indication on the trace stream is blocked regardless of the value programmed in this bit. |
| FlushMan | 6 | rwNormal read/write | 0x0 | Manually generate a flush of the system. Setting this bit causes a flush to be generated. If TraceCaptEn bit in CTL register is 0, then writes to this bit are ignored. In Circular buffer mode and Hardware-FIFO mode, this bit is cleared automatically when AFREADYS is sampled HIGH. In Software-FIFO mode, this bit is cleared when the flush data is written to trace memory. This bit is clear on reset. |
| FOnTrigEvt | 5 | rwNormal read/write | 0x0 | Setting this bit generates a flush when a Trigger event occurs. A trigger event is said to have occurred when the Formatter has written the set number of datawords (as programmed in the TRG register) into the trace memory after the occurrence of either a rising edge on the TRIGIN input or a trigger packet in the incoming trace stream (ATID = 7h7D). This bit is clear on reset. This bit is not supported in Software-read-FIFO mode or Hardware-read-FIFO mode because in FIFO mode, the TMC is a trace link rather than a trace sink and trigger events are related to trace sink functionality. |
| FOnFlIn | 4 | rwNormal read/write | 0x0 | Setting this bit enables the detection of transitions on the FLUSHIN input by the TMC. If this bit is set and the Formatter has not already stopped, a rising edge on FLUSHIN initiates a flush request. This bit is clear on reset. |
| EnTI | 1 | rwNormal read/write | 0x0 | Setting this bit enables the insertion of triggers in the formatted trace stream. A trigger is indicated by inserting one byte of data 8h00 with ATID 7h7D in the trace stream. Trigger indication on the trace stream is additionally controlled by the register bits TrigOnFl, TrigOnTrigEvt and TrigOnTrigIn in the FFCR register, 0x304. This bit can only be changed when TMCReady=1 and TraceCaptEn=0. This bit takes effect only when the EnFt register bit in this register is set. If EnTI bit is set to 1 when EnFt is 0, it results in formatting being enabled. This bit is clear on reset. |
| EnFt | 0 | rwNormal read/write | 0x0 | If this bit is set, formatting is enabled. This bit is clear on reset. This bit is ignored when in Disabled state (TraceCaptEn=0 and TMCReady=1).If this bit is cleared, formatting is disabled. Incoming trace data is assumed to be from a single trace source. If multiple ATIDs are received by the TMC when trace capture is enabled and the formatter is disabled, it will result in interleaving of trace data. Disabling of formatting is deprecated and is supported in the TMC for backwards-compatibility with earlier versions of the ETB. Hence, disabling of formatting is supported only in Circular Buffer mode. Features in the TMC such as the FIFO modes and the DrainBuffer bit that are not part of the earlier versions of the ETB do not support disabling of formatting. If EnTI bit is set to 1 when EnFt is 0, it results in formatting being enabled. If the TMC is enabled in a mode other than Circular Buffer mode with EnFt 0, it will result in formatting being enabled. Attempting to write to this bit when TMCReady=0 or TraceCaptEn=1 will result in Unpredictable behavior. |