FFLR (R5_ETM_0) Register Description
| Register Name | FFLR |
|---|---|
| Offset Address | 0x000000002C |
| Absolute Address | 0x00FEBFC02C (CORESIGHT_R5_ETM_0) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | FIFOFULL Level Register |
FFLR (R5_ETM_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Level | 7:0 | rwNormal read/write | 0 | The number of bytes left in the FIFO, below which the FIFOFULL or SuppressData signal is asserted. For example, setting this value to 15 causes data trace suppression or processor stalling, if enabled, when there are less than 15 free bytes in the FIFO. |