FFSR (ETF4K) Register Description
Register Name | FFSR |
---|---|
Offset Address | 0x0000000300 |
Absolute Address | 0x00FE940300 (CORESIGHT_SOC_ETF_1) |
Width | 32 |
Type | roRead-only |
Reset Value | 0x00000000 |
Description | This register indicates the status of the Formatter and the status of Flush request. |
FFSR (ETF4K) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
FtStopped | 1 | roRead-only | 0x0 | This bit behaves the same way as the FtEmpty bit in the STS register, 0x00C. The FtStopped bit is deprecated and is present in this register to support backwards-compatibility with earlier versions of the ETB. |
FlInProg | 0 | roRead-only | 0x0 | This bit indicates whether the TMC is currently processing a flush on the ATB slave port. This bit reflects the status of the AFVALIDS output. In the ETB or ETR configurations, the flush initiation is controlled by the flush-control bits in the FFCR register. In the ETF configuration, the flush request could additionally be from the ATB Master port. |