FFSR (ETF4K) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

FFSR (ETF4K) Register Description

Register NameFFSR
Offset Address0x0000000300
Absolute Address 0x00FE940300 (CORESIGHT_SOC_ETF_1)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionThis register indicates the status of the Formatter and the status of Flush request.

FFSR (ETF4K) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
FtStopped 1roRead-only0x0This bit behaves the same way as the FtEmpty bit in the STS register, 0x00C. The FtStopped bit is deprecated and is present in this register to support backwards-compatibility with earlier versions of the ETB.
FlInProg 0roRead-only0x0This bit indicates whether the TMC is currently processing a flush on the ATB slave port. This bit reflects the status of the AFVALIDS output. In the ETB or ETR configurations, the flush initiation is controlled by the flush-control bits in the FFCR register. In the ETF configuration, the flush request could additionally be from the ATB Master port.