FFSR (TPIU) Register Description
| Register Name | FFSR |
|---|---|
| Offset Address | 0x0000000300 |
| Absolute Address | 0x00FE980300 (CORESIGHT_SOC_TPIU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | This register indicates the current status of the formatter and flush features available in the TPIU. |
FFSR (TPIU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TCPresent | 2 | roRead-only | 0 | Indicates whether the tracectl pin is available for use.If this bit is set then tracectl is present. If no tracectl pin is available, that is, this bit is zero, then the data formatter must be used and only in continuous mode.This is constrained by the CSTPIU_TRACECTL_VAL Verilog `define, which is not user modifiable, and the external tie-off tpctl. If either constraint reports zero/LOW then no tracectl is present and this inability to use the pin is reflected in this register. |
| FtStopped | 1 | roRead-only | 0 | The formatter has received a stop request signal and all trace data and post-amble has been output. Any more trace data on the ATB interface is ignored and atreadys goes HIGH. |
| FlInProg | 0 | roRead-only | 0x0 | This is an indication of the current state of afvalids. |