FPD_GPV Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

FPD_GPV Module Description

Module Name	FPD_GPV Module
Modules of this Type	FPD_GPV
Base Addresses	0x00FD700000 (FPD_GPV)
Description	FPD GPV Module

FPD_GPV Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
periph_id_4	0x0000001FD0	32	roRead-only	0x00000004	4KB count, JEP106 continuation code
periph_id_5	0x0000001FD4	32	roRead-only	0x00000000	Reserved
periph_id_6	0x0000001FD8	32	roRead-only	0x00000000	Reserved
periph_id_7	0x0000001FDC	32	roRead-only	0x00000000	Reserved
periph_id_0	0x0000001FE0	32	roRead-only	0x00000000	Part Number [7:0]
periph_id_1	0x0000001FE4	32	roRead-only	0x000000B4	JEP106[3:0], part number [11:8]
periph_id_2	0x0000001FE8	32	roRead-only	0x0000002B	Revision, JEP106 code flag, JEP106[6:4]
periph_id_3	0x0000001FEC	32	roRead-only	0x00000000	You can set this using the AMBA Designer Graphical User Interface (GUI)
comp_id_0	0x0000001FF0	32	roRead-only	0x0000000D	Preamble
comp_id_1	0x0000001FF4	32	roRead-only	0x000000F0	Generic IP component class, preamble
comp_id_2	0x0000001FF8	32	roRead-only	0x00000005	Preamble
comp_id_3	0x0000001FFC	32	roRead-only	0x000000B1	Preamble
intfpd_intlpd_ib_fn_mod_iss_bm	0x0000002008	32	rwNormal read/write	0x00000000	Bus matrix issuing functionality modification register
intfpd_intlpd_ib_fn_mod2	0x0000002024	32	rwNormal read/write	0x00000000	This register is only present if upsizing or downsizing happens
intfpd_intlpd_ib_fn_mod	0x0000002108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
intfpdcci_intfpdmain_ib_fn_mod	0x0000042108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
intfpdcci_intfpdmain_ib_qos_cntl	0x000004210C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
intfpdcci_intfpdmain_ib_max_ot	0x0000042110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
intfpdcci_intfpdmain_ib_max_comb_ot	0x0000042114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
intfpdcci_intfpdmain_ib_aw_p	0x0000042118	32	rwNormal read/write	0x00000000	AW channel peak rate
intfpdcci_intfpdmain_ib_aw_b	0x000004211C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
intfpdcci_intfpdmain_ib_aw_r	0x0000042120	32	rwNormal read/write	0x00000000	AW channel average rate
intfpdcci_intfpdmain_ib_ar_p	0x0000042124	32	rwNormal read/write	0x00000000	AR channel peak rate
intfpdcci_intfpdmain_ib_ar_b	0x0000042128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
intfpdcci_intfpdmain_ib_ar_r	0x000004212C	32	rwNormal read/write	0x00000000	AR channel average rate
intfpdsmmutbu3_intfpdmain_fn_mod	0x0000043108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
intfpdsmmutbu3_intfpdmain_qos_cntl	0x000004310C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
intfpdsmmutbu3_intfpdmain_max_ot	0x0000043110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
intfpdsmmutbu3_intfpdmain_max_comb_ot	0x0000043114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
intfpdsmmutbu3_intfpdmain_aw_p	0x0000043118	32	rwNormal read/write	0x00000000	AW channel peak rate
intfpdsmmutbu3_intfpdmain_aw_b	0x000004311C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
intfpdsmmutbu3_intfpdmain_aw_r	0x0000043120	32	rwNormal read/write	0x00000000	AW channel average rate
intfpdsmmutbu3_intfpdmain_ar_p	0x0000043124	32	rwNormal read/write	0x00000000	AR channel peak rate
intfpdsmmutbu3_intfpdmain_ar_b	0x0000043128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
intfpdsmmutbu3_intfpdmain_ar_r	0x000004312C	32	rwNormal read/write	0x00000000	AR channel average rate
intfpdsmmutbu4_intfpdmain_fn_mod	0x0000044108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
intfpdsmmutbu4_intfpdmain_qos_cntl	0x000004410C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
intfpdsmmutbu4_intfpdmain_max_ot	0x0000044110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
intfpdsmmutbu4_intfpdmain_max_comb_ot	0x0000044114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
intfpdsmmutbu4_intfpdmain_aw_p	0x0000044118	32	rwNormal read/write	0x00000000	AW channel peak rate
intfpdsmmutbu4_intfpdmain_aw_b	0x000004411C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
intfpdsmmutbu4_intfpdmain_aw_r	0x0000044120	32	rwNormal read/write	0x00000000	AW channel average rate
intfpdsmmutbu4_intfpdmain_ar_p	0x0000044124	32	rwNormal read/write	0x00000000	AR channel peak rate
intfpdsmmutbu4_intfpdmain_ar_b	0x0000044128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
intfpdsmmutbu4_intfpdmain_ar_r	0x000004412C	32	rwNormal read/write	0x00000000	AR channel average rate
afifm0M_intfpd_fn_mod	0x0000045108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
afifm0M_intfpd_qos_cntl	0x000004510C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
afifm0M_intfpd_max_ot	0x0000045110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
afifm0M_intfpd_max_comb_ot	0x0000045114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
afifm0M_intfpd_aw_p	0x0000045118	32	rwNormal read/write	0x00000000	AW channel peak rate
afifm0M_intfpd_aw_b	0x000004511C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
afifm0M_intfpd_aw_r	0x0000045120	32	rwNormal read/write	0x00000000	AW channel average rate
afifm0M_intfpd_ar_p	0x0000045124	32	rwNormal read/write	0x00000000	AR channel peak rate
afifm0M_intfpd_ar_b	0x0000045128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
afifm0M_intfpd_ar_r	0x000004512C	32	rwNormal read/write	0x00000000	AR channel average rate
afifm1M_intfpd_fn_mod	0x0000046108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
afifm1M_intfpd_qos_cntl	0x000004610C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
afifm1M_intfpd_max_ot	0x0000046110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
afifm1M_intfpd_max_comb_ot	0x0000046114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
afifm1M_intfpd_aw_p	0x0000046118	32	rwNormal read/write	0x00000000	AW channel peak rate
afifm1M_intfpd_aw_b	0x000004611C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
afifm1M_intfpd_aw_r	0x0000046120	32	rwNormal read/write	0x00000000	AW channel average rate
afifm1M_intfpd_ar_p	0x0000046124	32	rwNormal read/write	0x00000000	AR channel peak rate
afifm1M_intfpd_ar_b	0x0000046128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
afifm1M_intfpd_ar_r	0x000004612C	32	rwNormal read/write	0x00000000	AR channel average rate
afifm2M_intfpd_fn_mod	0x0000047108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
afifm2M_intfpd_qos_cntl	0x000004710C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
afifm2M_intfpd_max_ot	0x0000047110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
afifm2M_intfpd_max_comb_ot	0x0000047114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
afifm2M_intfpd_aw_p	0x0000047118	32	rwNormal read/write	0x00000000	AW channel peak rate
afifm2M_intfpd_aw_b	0x000004711C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
afifm2M_intfpd_aw_r	0x0000047120	32	rwNormal read/write	0x00000000	AW channel average rate
afifm2M_intfpd_ar_p	0x0000047124	32	rwNormal read/write	0x00000000	AR channel peak rate
afifm2M_intfpd_ar_b	0x0000047128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
afifm2M_intfpd_ar_r	0x000004712C	32	rwNormal read/write	0x00000000	AR channel average rate
intfpdsmmutbu5_intfpdmain_fn_mod	0x0000048108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
intfpdsmmutbu5_intfpdmain_qos_cntl	0x000004810C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
intfpdsmmutbu5_intfpdmain_max_ot	0x0000048110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
intfpdsmmutbu5_intfpdmain_max_comb_ot	0x0000048114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
intfpdsmmutbu5_intfpdmain_aw_p	0x0000048118	32	rwNormal read/write	0x00000000	AW channel peak rate
intfpdsmmutbu5_intfpdmain_aw_b	0x000004811C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
intfpdsmmutbu5_intfpdmain_aw_r	0x0000048120	32	rwNormal read/write	0x00000000	AW channel average rate
intfpdsmmutbu5_intfpdmain_ar_p	0x0000048124	32	rwNormal read/write	0x00000000	AR channel peak rate
intfpdsmmutbu5_intfpdmain_ar_b	0x0000048128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
intfpdsmmutbu5_intfpdmain_ar_r	0x000004812C	32	rwNormal read/write	0x00000000	AR channel average rate
dp_intfpd_ib_fn_mod	0x0000049108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
dp_intfpd_ib_qos_cntl	0x000004910C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
dp_intfpd_ib_max_ot	0x0000049110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
dp_intfpd_ib_max_comb_ot	0x0000049114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
dp_intfpd_ib_aw_p	0x0000049118	32	rwNormal read/write	0x00000000	AW channel peak rate
dp_intfpd_ib_aw_b	0x000004911C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
dp_intfpd_ib_aw_r	0x0000049120	32	rwNormal read/write	0x00000000	AW channel average rate
dp_intfpd_ib_ar_p	0x0000049124	32	rwNormal read/write	0x00000000	AR channel peak rate
dp_intfpd_ib_ar_b	0x0000049128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
dp_intfpd_ib_ar_r	0x000004912C	32	rwNormal read/write	0x00000000	AR channel average rate
afifm3M_intfpd_fn_mod	0x000004A108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
afifm3M_intfpd_qos_cntl	0x000004A10C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
afifm3M_intfpd_max_ot	0x000004A110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
afifm3M_intfpd_max_comb_ot	0x000004A114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
afifm3M_intfpd_aw_p	0x000004A118	32	rwNormal read/write	0x00000000	AW channel peak rate
afifm3M_intfpd_aw_b	0x000004A11C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
afifm3M_intfpd_aw_r	0x000004A120	32	rwNormal read/write	0x00000000	AW channel average rate
afifm3M_intfpd_ar_p	0x000004A124	32	rwNormal read/write	0x00000000	AR channel peak rate
afifm3M_intfpd_ar_b	0x000004A128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
afifm3M_intfpd_ar_r	0x000004A12C	32	rwNormal read/write	0x00000000	AR channel average rate
afifm4M_intfpd_fn_mod	0x000004B108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
afifm4M_intfpd_qos_cntl	0x000004B10C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
afifm4M_intfpd_max_ot	0x000004B110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
afifm4M_intfpd_max_comb_ot	0x000004B114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
afifm4M_intfpd_aw_p	0x000004B118	32	rwNormal read/write	0x00000000	AW channel peak rate
afifm4M_intfpd_aw_b	0x000004B11C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
afifm4M_intfpd_aw_r	0x000004B120	32	rwNormal read/write	0x00000000	AW channel average rate
afifm4M_intfpd_ar_p	0x000004B124	32	rwNormal read/write	0x00000000	AR channel peak rate
afifm4M_intfpd_ar_b	0x000004B128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
afifm4M_intfpd_ar_r	0x000004B12C	32	rwNormal read/write	0x00000000	AR channel average rate
afifm5M_intfpd_fn_mod	0x000004C108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
afifm5M_intfpd_qos_cntl	0x000004C10C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
afifm5M_intfpd_max_ot	0x000004C110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
afifm5M_intfpd_max_comb_ot	0x000004C114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
afifm5M_intfpd_aw_p	0x000004C118	32	rwNormal read/write	0x00000000	AW channel peak rate
afifm5M_intfpd_aw_b	0x000004C11C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
afifm5M_intfpd_aw_r	0x000004C120	32	rwNormal read/write	0x00000000	AW channel average rate
afifm5M_intfpd_ar_p	0x000004C124	32	rwNormal read/write	0x00000000	AR channel peak rate
afifm5M_intfpd_ar_b	0x000004C128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
afifm5M_intfpd_ar_r	0x000004C12C	32	rwNormal read/write	0x00000000	AR channel average rate
gpu_intfpd_ib_read_qos	0x000004D100	32	rwNormal read/write	0x00000000	Read channel QoS value
gpu_intfpd_ib_write_qos	0x000004D104	32	rwNormal read/write	0x00000000	Write channel QoS value
gpu_intfpd_ib_fn_mod	0x000004D108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
gpu_intfpd_ib_qos_cntl	0x000004D10C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
gpu_intfpd_ib_max_ot	0x000004D110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
gpu_intfpd_ib_max_comb_ot	0x000004D114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
gpu_intfpd_ib_aw_p	0x000004D118	32	rwNormal read/write	0x00000000	AW channel peak rate
gpu_intfpd_ib_aw_b	0x000004D11C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
gpu_intfpd_ib_aw_r	0x000004D120	32	rwNormal read/write	0x00000000	AW channel average rate
gpu_intfpd_ib_ar_p	0x000004D124	32	rwNormal read/write	0x00000000	AR channel peak rate
gpu_intfpd_ib_ar_b	0x000004D128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
gpu_intfpd_ib_ar_r	0x000004D12C	32	rwNormal read/write	0x00000000	AR channel average rate
pcieM_intfpd_ib_fn_mod2	0x000004E024	32	rwNormal read/write	0x00000000	This register is only present if upsizing or downsizing happens
pcieM_intfpd_ib_read_qos	0x000004E100	32	rwNormal read/write	0x00000000	Read channel QoS value
pcieM_intfpd_ib_write_qos	0x000004E104	32	rwNormal read/write	0x00000000	Write channel QoS value
pcieM_intfpd_ib_fn_mod	0x000004E108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
pcieM_intfpd_ib_qos_cntl	0x000004E10C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
pcieM_intfpd_ib_max_ot	0x000004E110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
pcieM_intfpd_ib_max_comb_ot	0x000004E114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
pcieM_intfpd_ib_aw_p	0x000004E118	32	rwNormal read/write	0x00000000	AW channel peak rate
pcieM_intfpd_ib_aw_b	0x000004E11C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
pcieM_intfpd_ib_aw_r	0x000004E120	32	rwNormal read/write	0x00000000	AW channel average rate
pcieM_intfpd_ib_ar_p	0x000004E124	32	rwNormal read/write	0x00000000	AR channel peak rate
pcieM_intfpd_ib_ar_b	0x000004E128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
pcieM_intfpd_ib_ar_r	0x000004E12C	32	rwNormal read/write	0x00000000	AR channel average rate
gdma_intfpd_ib_fn_mod2	0x000004F024	32	rwNormal read/write	0x00000000	This register is only present if upsizing or downsizing happens
gdma_intfpd_ib_fn_mod	0x000004F108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
gdma_intfpd_ib_qos_cntl	0x000004F10C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
gdma_intfpd_ib_max_ot	0x000004F110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
gdma_intfpd_ib_max_comb_ot	0x000004F114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
gdma_intfpd_ib_aw_p	0x000004F118	32	rwNormal read/write	0x00000000	AW channel peak rate
gdma_intfpd_ib_aw_b	0x000004F11C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
gdma_intfpd_ib_aw_r	0x000004F120	32	rwNormal read/write	0x00000000	AW channel average rate
gdma_intfpd_ib_ar_p	0x000004F124	32	rwNormal read/write	0x00000000	AR channel peak rate
gdma_intfpd_ib_ar_b	0x000004F128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
gdma_intfpd_ib_ar_r	0x000004F12C	32	rwNormal read/write	0x00000000	AR channel average rate
sataM_intfpd_ib_fn_mod2	0x0000050024	32	rwNormal read/write	0x00000000	This register is only present if upsizing or downsizing happens
sataM_intfpd_ib_read_qos	0x0000050100	32	rwNormal read/write	0x00000000	Read channel QoS value
sataM_intfpd_ib_write_qos	0x0000050104	32	rwNormal read/write	0x00000000	Write channel QoS value
sataM_intfpd_ib_fn_mod	0x0000050108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
sataM_intfpd_ib_qos_cntl	0x000005010C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
sataM_intfpd_ib_max_ot	0x0000050110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
sataM_intfpd_ib_max_comb_ot	0x0000050114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
sataM_intfpd_ib_aw_p	0x0000050118	32	rwNormal read/write	0x00000000	AW channel peak rate
sataM_intfpd_ib_aw_b	0x000005011C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
sataM_intfpd_ib_aw_r	0x0000050120	32	rwNormal read/write	0x00000000	AW channel average rate
sataM_intfpd_ib_ar_p	0x0000050124	32	rwNormal read/write	0x00000000	AR channel peak rate
sataM_intfpd_ib_ar_b	0x0000050128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
sataM_intfpd_ib_ar_r	0x000005012C	32	rwNormal read/write	0x00000000	AR channel average rate
coresightM_intfpd_ib_fn_mod2	0x0000052024	32	rwNormal read/write	0x00000000	This register is only present if upsizing or downsizing happens
coresightM_intfpd_ib_read_qos	0x0000052100	32	rwNormal read/write	0x00000000	Read channel QoS value
coresightM_intfpd_ib_write_qos	0x0000052104	32	rwNormal read/write	0x00000000	Write channel QoS value
coresightM_intfpd_ib_fn_mod	0x0000052108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
coresightM_intfpd_ib_qos_cntl	0x000005210C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
coresightM_intfpd_ib_max_ot	0x0000052110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
coresightM_intfpd_ib_max_comb_ot	0x0000052114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
coresightM_intfpd_ib_aw_p	0x0000052118	32	rwNormal read/write	0x00000000	AW channel peak rate
coresightM_intfpd_ib_aw_b	0x000005211C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
coresightM_intfpd_ib_aw_r	0x0000052120	32	rwNormal read/write	0x00000000	AW channel average rate
coresightM_intfpd_ib_ar_p	0x0000052124	32	rwNormal read/write	0x00000000	AR channel peak rate
coresightM_intfpd_ib_ar_b	0x0000052128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
coresightM_intfpd_ib_ar_r	0x000005212C	32	rwNormal read/write	0x00000000	AR channel average rate
ib2_fn_mod_iss_bm	0x00000C2008	32	rwNormal read/write	0x00000000	Bus matrix issuing functionality modification register
ib2_fn_mod	0x00000C2108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
ib2_qos_cntl	0x00000C210C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
ib2_max_ot	0x00000C2110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
ib2_max_comb_ot	0x00000C2114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
ib2_aw_p	0x00000C2118	32	rwNormal read/write	0x00000000	AW channel peak rate
ib2_aw_b	0x00000C211C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
ib2_aw_r	0x00000C2120	32	rwNormal read/write	0x00000000	AW channel average rate
ib2_ar_p	0x00000C2124	32	rwNormal read/write	0x00000000	AR channel peak rate
ib2_ar_b	0x00000C2128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
ib2_ar_r	0x00000C212C	32	rwNormal read/write	0x00000000	AR channel average rate
ib6_fn_mod_iss_bm	0x00000C3008	32	rwNormal read/write	0x00000000	Bus matrix issuing functionality modification register
ib6_fn_mod2	0x00000C3024	32	rwNormal read/write	0x00000000	This register is only present if upsizing or downsizing happens
ib6_fn_mod	0x00000C3108	32	rwNormal read/write	0x00000000	Issuing functionality modification register
ib6_qos_cntl	0x00000C310C	32	rwNormal read/write	0x00000000	The QoS control register contains the enable bits for all the regulators.
ib6_max_ot	0x00000C3110	32	rwNormal read/write	0x00000000	Maximum number of outstanding transactions
ib6_max_comb_ot	0x00000C3114	32	rwNormal read/write	0x00000000	Maximum number of combined outstanding transactions
ib6_aw_p	0x00000C3118	32	rwNormal read/write	0x00000000	AW channel peak rate
ib6_aw_b	0x00000C311C	32	rwNormal read/write	0x00000000	AW channel burstiness allowance
ib6_aw_r	0x00000C3120	32	rwNormal read/write	0x00000000	AW channel average rate
ib6_ar_p	0x00000C3124	32	rwNormal read/write	0x00000000	AR channel peak rate
ib6_ar_b	0x00000C3128	32	rwNormal read/write	0x00000000	AR channel burstiness allowance
ib6_ar_r	0x00000C312C	32	rwNormal read/write	0x00000000	AR channel average rate