FSCR (TPIU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

FSCR (TPIU) Register Description

Register NameFSCR
Offset Address0x0000000308
Absolute Address 0x00FE980308 (CORESIGHT_SOC_TPIU)
Width32
TyperwNormal read/write
Reset Value0x00000040
DescriptionThe Formatter Synchronization Counter Register enables effective use on different sized Trace Port Analyzers (TPAs) without wasting large amounts of the storage capacity of the capture device.This counter is the number of formatter frames since the last synchronization packet of 128 bits, and is a 12-bit counter with a maximum count value of 4096. This equates to synchronization every 65536 bytes, that is, 4096 packets x 16 bytes per packet. The default is set up for a synchronization packet every 1024 bytes, that is, every 64 formatter frames.If the formatter has been configured for continuous mode, full and half-word sync frames are inserted during normal operation. Under these circumstances the count value represents the maximum number of complete frames between full synchronization packets.

FSCR (TPIU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CycCount11:0rwNormal read/write0x4012-bit counter value to indicate the number of complete frames between full synchronization packets. Default value is 64 (0x40).