FUNNEL4P Module Description
| Module Name | FUNNEL4P Module |
|---|---|
| Modules of this Type | CORESIGHT_SOC_FUNN_1, CORESIGHT_SOC_FUNN_2 |
| Base Addresses |
0x00FE920000 (CORESIGHT_SOC_FUNN_1) 0x00FE930000 (CORESIGHT_SOC_FUNN_2) |
| Description | Four-Port CoreSight Funnel |
FUNNEL4P Module Register Summary
| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| Ctrl_Reg | 0x0000000000 | 32 | rwNormal read/write | 0x00000000 | The Funnel Control Register enables the slave ports and defines the hold time of the slave ports. Hold time refers to the number of transactions that are output on the funnel master port from the same slave while that slave port atvalidsx is HIGH. Hold time does not refer to clock cycles in this context |
| Priority_Ctrl_Reg | 0x0000000004 | 32 | rwNormal read/write | 0x00000000 | The Priority Control Register defines the order in which inputs are selected. Each 3-bit field represents a priority for each particular slave interface. Location 0 has the priority value for the first slave port. Location 1 is the priority value for the second slave port, Location 2 is the third, down to location 7, which has the priority value of the eighth slave port. Values represent the priority value for each port number. If you want to give highest priority to a particular slave port, the corresponding port must be programmed with the lowest value. Typically this is likely to be a port that has more important data or that has a small FIFO and is therefore likely to overflow. If you want to give lowest priority to a particular slave port, the corresponding slave port must be programmed with the highest value. Typically this is likely to be a device that has a large FIFO that is less likely to overflow or a source that has information that is of lower importance. |
| ITATBDATA0 | 0x0000000EEC | 32 | rwNormal read/write | 0x00000000 | The Integration Test ATB Data 0 Register performs different functions depending on whether the access is a read or a write: A write outputs data on byte boundaries of ATDATAM. A read returns the data from ATDATASn, where n is defined by the status of the Funnel Control register at 0x000. The read data is only valid when ATVALIDSn is HIGH. |
| ITATBCTR2 | 0x0000000EF0 | 32 | rwNormal read/write | 0x00000000 | The Integration Test ATB Control 2 Register performs different functions depending on whether the access is a read or a write: * A write outputs data on atreadysn, where n is defined by the status of the ATB Funnel Control Register at 0x000 * A read returns the data from atreadym. |
| ITATBCTR1 | 0x0000000EF4 | 32 | rwNormal read/write | 0x00000000 | The Integration Test ATB Control 1 Register performs different functions depending on whether the access is a read or a write: * a write sets the value of the atidm. * a read returns the value of the atidmn signals, where n is defined by the status of the Control register at 0x000. |
| ITATBCTR0 | 0x0000000EF8 | 32 | rwNormal read/write | 0x00000000 | The Integration Test ATB Control 0 Register performs different functions depending on whether the access is a read or a write: * a write sets the value of the atvalidm. * a read returns the value of the atvalidsn signals, where n is defined by the status of the Control register at 0x000. |
| ITCTRL | 0x0000000F00 | 32 | rwNormal read/write | 0x00000000 | This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving Note When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection. |
| CLAIMSET | 0x0000000FA0 | 32 | rwNormal read/write | 0x00000000 | This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read. |
| CLAIMCLR | 0x0000000FA4 | 32 | rwNormal read/write | 0x00000000 | This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read. |
| LAR | 0x0000000FB0 | 32 | woWrite-only | 0x00000000 | This is used to enable write access to device registers. |
| LSR | 0x0000000FB4 | 32 | roRead-only | 0x00000000 | This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. This register must always be present although there might not be any lock-access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register 0xFB0 |
| AUTHSTATUS | 0x0000000FB8 | 32 | roRead-only | 0x00000000 | Reports the required security level and current status of those enables. Where functionality changes on a given security level then this change in status must be reported in this register |
| DEVID | 0x0000000FC8 | 32 | roRead-only | 0x00000000 | This indicates the capabilities of the CoreSight Funnel. |
| DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000000 | It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information. |
| PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator. |
| PIDR5 | 0x0000000FD4 | 32 | rwNormal read/write | 0x00000000 | Reserved |
| PIDR6 | 0x0000000FD8 | 32 | rwNormal read/write | 0x00000000 | Reserved |
| PIDR7 | 0x0000000FDC | 32 | rwNormal read/write | 0x00000000 | Reserved |
| PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number. |
| PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity. |
| PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision. |
| PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields. |
| CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |
| CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. This register also indicates the component class. |
| CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |
| CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x00000000 | A component identification register, that indicates that the identification registers are present. |