GEM Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

GEM Module Description

Module Name	GEM Module
Modules of this Type	GEM0, GEM1, GEM2, GEM3
Base Addresses	0x00FF0B0000 (GEM0) 0x00FF0C0000 (GEM1) 0x00FF0D0000 (GEM2) 0x00FF0E0000 (GEM3)
Description	Gigabit Ethernet Controller

GEM Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
network_control	0x0000000000	32	mixedMixed types. See bit-field details.	0x00000000	The network control register contains general MAC control functions for both receiver and transmitter.
network_config	0x0000000004	32	rwNormal read/write	0x00280000	The network configuration register contains functions for setting the mode of operation for the Gigabit Ethernet MAC.
network_status	0x0000000008	32	roRead-only	0x00000004	The network status register returns status information with respect to the PHY management interface.
dma_config	0x0000000010	32	mixedMixed types. See bit-field details.	0x00020784	DMA Configuration Register
transmit_status	0x0000000014	32	mixedMixed types. See bit-field details.	0x00000000	This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
receive_q_ptr	0x0000000018	32	mixedMixed types. See bit-field details.	0x00000000	Start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of system bus operation, the receive descriptors must be aligned at 64-bit boundaries for each pair of 32-bit descriptors.
transmit_q_ptr	0x000000001C	32	mixedMixed types. See bit-field details.	0x00000000	Start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of system bus operation, the transmit descriptors must be aligned at 64-bit boundaries for each pair of 32-bit descriptors.
receive_status	0x0000000020	32	mixedMixed types. See bit-field details.	0x00000000	This register, when read provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
int_status	0x0000000024	32	mixedMixed types. See bit-field details.	0x00000000	Interrupt Status - non-priority queing.
int_enable	0x0000000028	32	mixedMixed types. See bit-field details.	0x00000000	At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
int_disable	0x000000002C	32	mixedMixed types. See bit-field details.	0x00000000	Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
int_mask	0x0000000030	32	roRead-only	0x3FFFFFFF	The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
phy_management	0x0000000034	32	rwNormal read/write	0x00000000	PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit-2 is set in the network status register. It takes about 125 LPD_LSBUS_CLK clock cycles to complete, when MDC is set for LPD_LSBUS_CLK divide by 2 in the network configuration register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. See Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits will be updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. For a description of MDC generation, see Network Configuration Register.
pause_time	0x0000000038	32	roRead-only	0x00000000	Received Pause Quantum Register
tx_pause_quantum	0x000000003C	32	mixedMixed types. See bit-field details.	0x0000FFFF	Transmit Pause Quantum Register
pbuf_txcutthru	0x0000000040	32	mixedMixed types. See bit-field details.	0x00000FFF	Partial store and forward is only applicable when using the the DMA configured in SRAM based packet buffer mode. It is also not available when using multi buffer frames. TX Partial Store and Forward
pbuf_rxcutthru	0x0000000044	32	mixedMixed types. See bit-field details.	0x00000FFF	RX Partial Store and Forward
jumbo_max_length	0x0000000048	32	mixedMixed types. See bit-field details.	0x00003FFF	Maximum Jumbo Frame Size.
external_fifo_interface	0x000000004C	32	mixedMixed types. See bit-field details.	0x00000000	External FIFO Interface Enable (only valid when gem_host_if_soft_select is defined)
axi_max_pipeline	0x0000000054	32	mixedMixed types. See bit-field details.	0x00000101	Used to set the maximum amnount of outstanding transactions on the AXI bus between AR / R channels and AW / W channels. Cannot be more than the depth of the configured AXI pipeline FIFO. Note: We recommend to use the default setting for this register.
hash_bottom	0x0000000080	32	rwNormal read/write	0x00000000	The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched framesHash Register Bottom [31:0]
hash_top	0x0000000084	32	rwNormal read/write	0x00000000	Hash Register Top 63:32
spec_add1_bottom	0x0000000088	32	rwNormal read/write	0x00000000	The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
spec_add1_top	0x000000008C	32	mixedMixed types. See bit-field details.	0x00000000	Specific Address Top
spec_add2_bottom	0x0000000090	32	rwNormal read/write	0x00000000	The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
spec_add2_top	0x0000000094	32	mixedMixed types. See bit-field details.	0x00000000	Specific Address Top
spec_add3_bottom	0x0000000098	32	rwNormal read/write	0x00000000	The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
spec_add3_top	0x000000009C	32	mixedMixed types. See bit-field details.	0x00000000	Specific Address Top
spec_add4_bottom	0x00000000A0	32	rwNormal read/write	0x00000000	The addresses stored in the specific address registers are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written.
spec_add4_top	0x00000000A4	32	mixedMixed types. See bit-field details.	0x00000000	Specific Address Top
spec_type1	0x00000000A8	32	mixedMixed types. See bit-field details.	0x00000000	Type ID Match 1
spec_type2	0x00000000AC	32	mixedMixed types. See bit-field details.	0x00000000	Type ID Match 2
spec_type3	0x00000000B0	32	mixedMixed types. See bit-field details.	0x00000000	Type ID Match 3
spec_type4	0x00000000B4	32	mixedMixed types. See bit-field details.	0x00000000	Type ID Match 4
wol_register	0x00000000B8	32	mixedMixed types. See bit-field details.	0x00000000	Wake on LAN Register
stretch_ratio	0x00000000BC	32	mixedMixed types. See bit-field details.	0x00000000	IPG stretch register
stacked_vlan	0x00000000C0	32	mixedMixed types. See bit-field details.	0x00000000	Stacked VLAN Register
tx_pfc_pause	0x00000000C4	32	mixedMixed types. See bit-field details.	0x00000000	Transmit PFC Pause Register
mask_add1_bottom	0x00000000C8	32	rwNormal read/write	0x00000000	Specific Address Mask 1 Bottom 31:0
mask_add1_top	0x00000000CC	32	mixedMixed types. See bit-field details.	0x00000000	Specific Address Mask 1 Top 47:32
dma_addr_or_mask	0x00000000D0	32	mixedMixed types. See bit-field details.	0x00000000	Receive DMA Data Buffer Address Mask
rx_ptp_unicast	0x00000000D4	32	rwNormal read/write	0x00000000	PTP RX unicast IP destination address
tx_ptp_unicast	0x00000000D8	32	rwNormal read/write	0x00000000	PTP TX unicast IP destination address
tsu_nsec_cmp	0x00000000DC	32	mixedMixed types. See bit-field details.	0x00000000	TSU timer comparison value nanoseconds
tsu_sec_cmp	0x00000000E0	32	rwNormal read/write	0x00000000	TSU timer comparison value seconds 31:0
tsu_msb_sec_cmp	0x00000000E4	32	mixedMixed types. See bit-field details.	0x00000000	TSU timer comparison value seconds 47:32
tsu_ptp_tx_msb_sec	0x00000000E8	32	roRead-only	0x00000000	PTP Event Frame Transmitted Seconds Register 47:32
tsu_ptp_rx_msb_sec	0x00000000EC	32	roRead-only	0x00000000	PTP Event Frame Received Seconds Register 47:32
tsu_peer_tx_msb_sec	0x00000000F0	32	roRead-only	0x00000000	PTP Peer Event Frame Transmitted Seconds Register 47:32
tsu_peer_rx_msb_sec	0x00000000F4	32	roRead-only	0x00000000	PTP Peer Event Frame Received Seconds Register 47:32
dpram_fill_dbg	0x00000000F8	32	mixedMixed types. See bit-field details.	0x00000000	The fill levels for the TX & RX packet buffers can be read using this register, including the fill level for each queue in the TX direction.
revision_reg	0x00000000FC	32	roRead-only	0x40070106	This register indicates a module identification number and module revision. The value of this register is read only as defined by `gem_revision_reg_value
octets_txed_bottom	0x0000000100	32	rwNormal read/write	0x00000000	These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. In order to reduce overall design area, the statistics registers may be optionally removed in the configuration file if they are deemed unnecsessary for a particular design. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. The statistics registers optionally have a snapshot capability which, when exercised, will simultaneously store and clear the current values of all the statistics registers into a snapshot register set in order to allow a consistent set of statistics to be read by the processor. The snapshot is controlled using bit 13 of the network control register. The read snapshot control indicated by bit 14 of the network control register determines whether the processor reads the snapshot registers (logic 1) or the incrementing registers (logic 0). The default GEM configuration does not support the snapshot capability. See Parameterization section under Implementation Application Notes for an explanation of how to enable this function. All the statistics registers are read only. For test purposes they may be written by setting bit 7 (Write Enable) in the network control register. Setting bit 6 (increment statistics) in the network control register causes all the statistics registers to increment by one, again for test purposes. Once a statistics register has been read, it is automatically cleared. When reading the octets transmitted and octets received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. The statistics register block contains the following registers. Octets Transmitted [31:0]
octets_txed_top	0x0000000104	32	mixedMixed types. See bit-field details.	0x00000000	Octets Transmitted 47:32
frames_txed_ok	0x0000000108	32	rwNormal read/write	0x00000000	Frames Transmitted
broadcast_txed	0x000000010C	32	rwNormal read/write	0x00000000	Broadcast Frames Transmitted
multicast_txed	0x0000000110	32	rwNormal read/write	0x00000000	Multicast Frames Transmitted
pause_frames_txed	0x0000000114	32	mixedMixed types. See bit-field details.	0x00000000	Pause Frames Transmitted
frames_txed_64	0x0000000118	32	rwNormal read/write	0x00000000	64 Byte Frames Transmitted
frames_txed_65	0x000000011C	32	rwNormal read/write	0x00000000	65 to 127 Byte Frames Transmitted
frames_txed_128	0x0000000120	32	rwNormal read/write	0x00000000	128 to 255 Byte Frames Transmitted
frames_txed_256	0x0000000124	32	rwNormal read/write	0x00000000	256 to 511 Byte Frames Transmitted
frames_txed_512	0x0000000128	32	rwNormal read/write	0x00000000	512 to 1023 Byte Frames Transmitted
frames_txed_1024	0x000000012C	32	rwNormal read/write	0x00000000	1024 to 1518 Byte Frames Transmitted
frames_txed_1519	0x0000000130	32	rwNormal read/write	0x00000000	Greater Than 1518 Byte Frames Transmitted
tx_underruns	0x0000000134	32	mixedMixed types. See bit-field details.	0x00000000	Transmit Under Runs
single_collisions	0x0000000138	32	mixedMixed types. See bit-field details.	0x00000000	Single Collision Frames
multiple_collisions	0x000000013C	32	mixedMixed types. See bit-field details.	0x00000000	Multiple Collision Frames
excessive_collisions	0x0000000140	32	mixedMixed types. See bit-field details.	0x00000000	Excessive Collisions
late_collisions	0x0000000144	32	mixedMixed types. See bit-field details.	0x00000000	Late Collisions
deferred_frames	0x0000000148	32	mixedMixed types. See bit-field details.	0x00000000	Deferred Transmission Frames
crs_errors	0x000000014C	32	mixedMixed types. See bit-field details.	0x00000000	Carrier Sense Errors
octets_rxed_bottom	0x0000000150	32	rwNormal read/write	0x00000000	Octets Received 31:0
octets_rxed_top	0x0000000154	32	mixedMixed types. See bit-field details.	0x00000000	Octets Received 47:32
frames_rxed_ok	0x0000000158	32	rwNormal read/write	0x00000000	Frames Received
broadcast_rxed	0x000000015C	32	rwNormal read/write	0x00000000	Broadcast Frames Received
multicast_rxed	0x0000000160	32	rwNormal read/write	0x00000000	Multicast Frames Received
pause_frames_rxed	0x0000000164	32	mixedMixed types. See bit-field details.	0x00000000	Pause Frames Received
frames_rxed_64	0x0000000168	32	rwNormal read/write	0x00000000	64 Byte Frames Received
frames_rxed_65	0x000000016C	32	rwNormal read/write	0x00000000	65 to 127 Byte Frames Received
frames_rxed_128	0x0000000170	32	rwNormal read/write	0x00000000	128 to 255 Byte Frames Received
frames_rxed_256	0x0000000174	32	rwNormal read/write	0x00000000	256 to 511 Byte Frames Received
frames_rxed_512	0x0000000178	32	rwNormal read/write	0x00000000	512 to 1023 Byte Frames Received
frames_rxed_1024	0x000000017C	32	rwNormal read/write	0x00000000	1024 to 1518 Byte Frames Received
frames_rxed_1519	0x0000000180	32	rwNormal read/write	0x00000000	1519 to maximum Byte Frames Received
undersize_frames	0x0000000184	32	mixedMixed types. See bit-field details.	0x00000000	Undersized Frames Received
excessive_rx_length	0x0000000188	32	mixedMixed types. See bit-field details.	0x00000000	Oversize Frames Received
rx_jabbers	0x000000018C	32	mixedMixed types. See bit-field details.	0x00000000	Jabbers Received
fcs_errors	0x0000000190	32	mixedMixed types. See bit-field details.	0x00000000	Frame Check Sequence Errors
rx_length_errors	0x0000000194	32	mixedMixed types. See bit-field details.	0x00000000	Length Field Frame Errors
rx_symbol_errors	0x0000000198	32	mixedMixed types. See bit-field details.	0x00000000	Receive Symbol Errors
alignment_errors	0x000000019C	32	mixedMixed types. See bit-field details.	0x00000000	Alignment Errors
rx_resource_errors	0x00000001A0	32	mixedMixed types. See bit-field details.	0x00000000	Receive Resource Errors
rx_overruns	0x00000001A4	32	mixedMixed types. See bit-field details.	0x00000000	Receive Overruns
rx_ip_ck_errors	0x00000001A8	32	mixedMixed types. See bit-field details.	0x00000000	IP Header Checksum Errors
rx_tcp_ck_errors	0x00000001AC	32	mixedMixed types. See bit-field details.	0x00000000	TCP Checksum Errors
rx_udp_ck_errors	0x00000001B0	32	mixedMixed types. See bit-field details.	0x00000000	UDP Checksum Errors
auto_flushed_pkts	0x00000001B4	32	mixedMixed types. See bit-field details.	0x00000000	Receive DMA Flushed Packets
tsu_timer_incr_sub_nsec	0x00000001BC	32	mixedMixed types. See bit-field details.	0x00000000	1588 Timer Increment Register sub nsec
tsu_timer_msb_sec	0x00000001C0	32	mixedMixed types. See bit-field details.	0x00000000	1588 Timer Seconds Register 47:32
tsu_strobe_msb_sec	0x00000001C4	32	roRead-only	0x00000000	1588 Timer Sync Strobe Seconds Register 47:32
tsu_strobe_sec	0x00000001C8	32	roRead-only	0x00000000	1588 Timer Sync Strobe Seconds Register 31:0
tsu_strobe_nsec	0x00000001CC	32	roRead-only	0x00000000	1588 Timer Sync Strobe Nanoseconds Register
tsu_timer_sec	0x00000001D0	32	rwNormal read/write	0x00000000	1588 Timer Seconds Register 31:0
tsu_timer_nsec	0x00000001D4	32	mixedMixed types. See bit-field details.	0x00000000	1588 Timer Nanoseconds Register
tsu_timer_adjust	0x00000001D8	32	mixedMixed types. See bit-field details.	0x00000000	This register returns all zeroes when read.
tsu_timer_incr	0x00000001DC	32	mixedMixed types. See bit-field details.	0x00000000	1588 Timer Increment Register
tsu_ptp_tx_sec	0x00000001E0	32	roRead-only	0x00000000	PTP Event Frame Transmitted Seconds Register 31:0
tsu_ptp_tx_nsec	0x00000001E4	32	roRead-only	0x00000000	PTP Event Frame Transmitted Nanoseconds Register
tsu_ptp_rx_sec	0x00000001E8	32	roRead-only	0x00000000	PTP Event Frame Received Seconds Register 31:0
tsu_ptp_rx_nsec	0x00000001EC	32	roRead-only	0x00000000	PTP Event Frame Received Nanoseconds Register
tsu_peer_tx_sec	0x00000001F0	32	roRead-only	0x00000000	PTP Peer Event Frame Transmitted Seconds Register 31:0
tsu_peer_tx_nsec	0x00000001F4	32	roRead-only	0x00000000	PTP Peer Event Frame Transmitted Nanoseconds Register
tsu_peer_rx_sec	0x00000001F8	32	roRead-only	0x00000000	PTP Peer Event Frame Received Seconds Register 31:0
tsu_peer_rx_nsec	0x00000001FC	32	roRead-only	0x00000000	PTP Peer Event Frame Received Nanoseconds Register
pcs_control	0x0000000200	32	mixedMixed types. See bit-field details.	0x00001040	Note:All PCS registers are defined in the IEEE 802.3 Standard. PCS Control RegisterThis register provides the main control functions with respect to the PCS.
pcs_status	0x0000000204	32	roRead-only	0x00000109	This register indicates general status information concerning the PCS.
pcs_phy_top_id	0x0000000208	32	roRead-only	0x00004007	The value of this register indicates the upper 16-bits of the PHYs identification code. This is a read-only register with a value defined by `gem_phy_id_top
pcs_phy_bot_id	0x000000020C	32	roRead-only	0x00000106	The value of this register indicates the lower 16-bits of the PHYs identification code. This is a read-only register with a value defined by `gem_phy_id_bot
pcs_an_adv	0x0000000210	32	mixedMixed types. See bit-field details.	0x00000020	The value of this register is used to transmit the base page of the GEM PCS capabilities. Note this is only valid for the default configuration where SGMII is not included in the GEM. In this case the registers is reserved. When SGMII is included, this register returns fixed 0x00000001 when read. SGMII specifies that the transmit configuration information sent from the MAC to the PHY is fixed with bit 14 set to 1 to indicate acknowledge, bit 0 set to 1 to indicate SGMII and all other bits set to 0.
pcs_an_lp_base	0x0000000214	32	roRead-only	0x00000000	For non SGMII (default) mode, the value of this register contains the link partners base page received information. This register is updated in the ABILITY_DETECT state of the PCS auto-negotiation state machine so bit 14 will only be set if the link partner is sending acknowledge while the PCS in this state. The register is not updated in the ACK_DETECT state. For SGMII mode, the contents of this register change to the one defined in the SGMII standard. The value of this register contains the link partners base page received information. In this case the link partner is the PHY connected by the SGMII.
pcs_an_exp	0x0000000218	32	roRead-only	0x00000004	This register contains auto-negotiation next page ability and page received information.
pcs_an_np_tx	0x000000021C	32	mixedMixed types. See bit-field details.	0x00000000	The value of this register is used to transmit the next page information for the GEM PCS. For next page exchange to work this register must be written within 10 ms of receiving a new page from the link partner. If the link partner is requesting next pages and the GEM has none or no more to send then this register should be written with the null message (0x2001). The value 0x0000 must not be written to this register.
pcs_an_lp_np	0x0000000220	32	roRead-only	0x00000000	This value of this register contains the next page received information from the link partner.
pcs_an_ext_status	0x000000023C	32	roRead-only	0x00008000	This register contains PCS auto-negotiation extended status information.
rx_lpi	0x0000000270	32	mixedMixed types. See bit-field details.	0x00000000	Received LPI transitions
rx_lpi_time	0x0000000274	32	rwNormal read/write	0x00000000	Received LPI time
tx_lpi	0x0000000278	32	mixedMixed types. See bit-field details.	0x00000000	Transmit LPI transitions
tx_lpi_time	0x000000027C	32	mixedMixed types. See bit-field details.	0x00000000	Transmit LPI time
designcfg_debug1	0x0000000280	32	roRead-only	0x0450011C	The defined parameterized options to configure the IP are read here.
designcfg_debug2	0x0000000284	32	roRead-only	0x73313FFF	Design Configuration Register 2
designcfg_debug3	0x0000000288	32	roRead-only	0x04000000	Design Configuration Register 3
designcfg_debug4	0x000000028C	32	roRead-only	0x00000000	Design Configuration Register 4
designcfg_debug5	0x0000000290	32	roRead-only	0x502F2744	Design Configuration Register 5
designcfg_debug6	0x0000000294	32	roRead-only	0x02510002	Design Configuration Register 6
designcfg_debug7	0x0000000298	32	roRead-only	0x00000000	Design Configuration Register 7
designcfg_debug8	0x000000029C	32	roRead-only	0x04040404	Design Configuration Register 8
designcfg_debug9	0x00000002A0	32	roRead-only	0x00000000	Design Configuration Register 9
designcfg_debug10	0x00000002A4	32	roRead-only	0x22242222	Design Configuration Register 10
int_q1_status	0x0000000400	32	mixedMixed types. See bit-field details.	0x00000000	Priority Queue Interrupt Status Register
transmit_q1_ptr	0x0000000440	32	mixedMixed types. See bit-field details.	0x00000000	Start address of the transmit buffer queue (transmit buffers descriptor list). The transmit buffer queue base address register must be initialized before transmit is started through bit 9 of the network control register. Once transmission has started, any write to the transmit buffer queue base address register is illegal and therefore ignored. Writing to the transmit buffer queue base address register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of the system bus operation, the transmit descriptors must be aligned at 64-bit boundaries for each pair of 32-bit descriptors is read from memory using a single bus access.
receive_q1_ptr	0x0000000480	32	mixedMixed types. See bit-field details.	0x00000000	Start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the network control register. Once reception is enabled, any write to the receive buffer queue base address register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. In terms of the system bus operation, the receive descriptors must be aligned at 64-bit boundaries and each pair of 32-bit descriptors is written to using a single 64-bit bus access.
dma_rxbuf_size_q1	0x00000004A0	32	mixedMixed types. See bit-field details.	0x00000002	Receive Buffer Queue Size
cbs_control	0x00000004BC	32	mixedMixed types. See bit-field details.	0x00000000	The IdleSlope value is defined as the rate of change of credit when a packet is waiting to be sent. This must not exceed the portTransmitRate which is dependent on the speed of operation, eg, portTranmsitRate: 1Gb/sec= 32h07735940,100Mb/sec = 32h017D7840, 10Mb/sec = 32h002625A0. If 50% of bandwidth was to be allocated to a particular queue in 1Gb/sec mode then the IdleSlope value for that queue would be calculated as 32h07735940/2. Note: Credit-Based Shaping should be disabled prior to updating the IdleSlope values.
upper_tx_q_base_addr	0x00000004C8	32	rwNormal read/write	0x00000000	Upper 32 bits of transmit buffer descriptor queue base address.
tx_bd_control	0x00000004CC	32	mixedMixed types. See bit-field details.	0x00000000	TX BD control register
rx_bd_control	0x00000004D0	32	mixedMixed types. See bit-field details.	0x00000000	RX BD control register
upper_rx_q_base_addr	0x00000004D4	32	rwNormal read/write	0x00000000	Upper 32 bits of receive buffer descriptor queue base address.
screening_type_1_register_0	0x0000000500	32	mixedMixed types. See bit-field details.	0x00000000	Screening type 1 registers are used to allocate two priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C.
screening_type_1_register_1	0x0000000504	32	mixedMixed types. See bit-field details.	0x00000000	Screening type 1 registers are used to allocate two priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C.
screening_type_1_register_2	0x0000000508	32	mixedMixed types. See bit-field details.	0x00000000	Screening type 1 registers are used to allocate two priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C.
screening_type_1_register_3	0x000000050C	32	mixedMixed types. See bit-field details.	0x00000000	Screening type 1 registers are used to allocate two priority queues to received frames based on certain IP or UDP fields of incoming frames. Firstly, when DS/TC match enable is set (bit 28), the DS (Differentiated Services) field of the received IPv4 header or TCfield (traffic class) of IPv6 headers are matched against bits 11:4. Secondly, when UDP port match enable is set (bit 29), the UDP Destination Port of the received UDP frame is matched against bits 27:12. Both UDP and DS/TC matching can be enabled simultaneously or individually. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 1 screening registers is configured in the gem defines file. Up to 16 type 1 screening registers have been allocated APB address space between 0x500 and 0x53C.
screening_type_2_register_0	0x0000000540	32	mixedMixed types. See bit-field details.	0x00000000	Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself.2) An enabled EtherType.3) An enabled Field Compare A. 4) An enabled Field Compare B. 5) An enabled Field Compare C. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C.
screening_type_2_register_1	0x0000000544	32	mixedMixed types. See bit-field details.	0x00000000	Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself.2) An enabled EtherType.3) An enabled Field Compare A. 4) An enabled Field Compare B. 5) An enabled Field Compare C. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C.
screening_type_2_register_2	0x0000000548	32	mixedMixed types. See bit-field details.	0x00000000	Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself.2) An enabled EtherType.3) An enabled Field Compare A. 4) An enabled Field Compare B. 5) An enabled Field Compare C. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C.
screening_type_2_register_3	0x000000054C	32	mixedMixed types. See bit-field details.	0x00000000	Screener Type 2 match registers allow a screen to be configured that is the combination of all or any of the following comparisons:1) An enabled VLAN Priority. A VLAN Priority match will be performed if the VLAN priority enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the screener type 2 register itself.2) An enabled EtherType.3) An enabled Field Compare A. 4) An enabled Field Compare B. 5) An enabled Field Compare C. If a match is successful, then the queue value programmed in bits 3:0 is allocated to the frame. The required number of Type 2 screening registers is configured in the gem defines file. Up to 16 type 2 screening registers have been allocated APB address space between 0x540 and 0x57C.
int_q1_enable	0x0000000600	32	mixedMixed types. See bit-field details.	0x00000000	At reset all interrupts are disabled. Writing a one to the relevant bit location enables the required interrupt. This register is write only and when read will return zero.
int_q1_disable	0x0000000620	32	mixedMixed types. See bit-field details.	0x00000000	Writing a 1 to the relevant bit location disables that particular interrupt. This register is write only and when read will return zero.
int_q1_mask	0x0000000640	32	roRead-only	0x00000CE6	The interrupt mask register is a read only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the interrupt enable register or set individually by writing to the interrupt disable register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the interrupt mask register. For test purposes there is a write-only function to this register that allows the bits in the interrupt status register to be set or cleared, regardless of the state of the mask register.
screening_type_2_ethertype_reg_0	0x00000006E0	32	mixedMixed types. See bit-field details.	0x00000000	Ethertype Register
screening_type_2_ethertype_reg_1	0x00000006E4	32	mixedMixed types. See bit-field details.	0x00000000	Ethertype Register
screening_type_2_ethertype_reg_2	0x00000006E8	32	mixedMixed types. See bit-field details.	0x00000000	Ethertype Register
screening_type_2_ethertype_reg_3	0x00000006EC	32	mixedMixed types. See bit-field details.	0x00000000	Ethertype Register
type2_compare_0_word_0	0x0000000700	32	rwNormal read/write	0x00000000	Compare A,B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value, is equal to the COMPARE Value. A 16 bit word comparison is done. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE and MASK. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and MASK. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the etherType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value its not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. The bit mapping for these registers is as follows:
type2_compare_0_word_1	0x0000000704	32	mixedMixed types. See bit-field details.	0x00000000	Type2 Compare Word 1
type2_compare_1_word_0	0x0000000708	32	rwNormal read/write	0x00000000	Compare A,B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value, is equal to the COMPARE Value. A 16 bit word comparison is done. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE and MASK. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and MASK. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the etherType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value its not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. The bit mapping for these registers is as follows:
type2_compare_1_word_1	0x000000070C	32	mixedMixed types. See bit-field details.	0x00000000	Type2 Compare Word 1
type2_compare_2_word_0	0x0000000710	32	rwNormal read/write	0x00000000	Compare A,B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value, is equal to the COMPARE Value. A 16 bit word comparison is done. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE and MASK. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and MASK. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the etherType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value its not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. The bit mapping for these registers is as follows:
type2_compare_2_word_1	0x0000000714	32	mixedMixed types. See bit-field details.	0x00000000	Type2 Compare Word 1
type2_compare_3_word_0	0x0000000718	32	rwNormal read/write	0x00000000	Compare A,B and C fields of the screener type 2 match register are pointers to a pool of up to 32 compare registers. If enabled the compare is true if the data at the OFFSET into the frame, ANDed with the MASK Value, is equal to the COMPARE Value. A 16 bit word comparison is done. The byte at the OFFSET number of bytes from the index start is compared thru bits 7:0 of the configured VALUE and MASK. The byte at the OFFSET number of bytes + 1 from the index start is compared thru bits 15:8 of the configured VALUE and MASK. The OFFSET can be configured to be from 0 to 127 bytes from either the start of the frame, the byte following the etherType field (last EtherType in the header if the frame is VLAN tagged), the byte following the IP header (IPv4 or IPv6) or from the byte following the start of the TCP/UDP header. The required number of Type 2 screening registers up to a maximum of 32 is configurable in the gem defines file and have been allocated APB address space between 0x700 and 0x7fc. Note. when using RX Partial Store and Forward mode and priority queues, the frame offset must be less than the Partial Store and Forward watermark. If the offset is higher than the watermark value its not possible to identify the priority queue before the frame is sent to the AMBA interface, and an incorrect priority queue may be used. The bit mapping for these registers is as follows:
type2_compare_3_word_1	0x000000071C	32	mixedMixed types. See bit-field details.	0x00000000	Type2 Compare Word 1