GEM2_REF_CTRL (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GEM2_REF_CTRL (CRL_APB) Register Description

Register NameGEM2_REF_CTRL
Offset Address0x0000000058
Absolute Address 0x00FF5E0058 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x00002500
DescriptionGEM 2 Clock Generator Config

GEM2_REF_CTRL (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:27rwNormal read/write0x0reserved
RX_CLKACT26rwNormal read/write0x0RX Channel Clock active control.
0: disable.
1: enable.
CLKACT25rwNormal read/write0x0Clock active control.
0: disable.
1: enable.
Reserved24:22rwNormal read/write0x0reserved
DIVISOR121:16rwNormal read/write0x06-bit divider.
Reserved15:14rwNormal read/write0x0reserved
DIVISOR013:8rwNormal read/write0x256-bit divider.
Reserved 7:3rwNormal read/write0x0reserved
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: IOPLL
010: RPLL
011: DPLL_CLK_TO_LPD